How to Reduce Maximum Power at RTL Stage?

How to Reduce Maximum Power at RTL Stage?
by Pawan Fangaria on 08-16-2014 at 8:30 am

Of course that reduction has to stay throughout the design cycle up to layout implementation and fabrication. Since the advent of high density, mega functionality SoC designs at advanced nodes and battery life critical devices played by our fingertips, the gap between SoC power requirement and actual SoC power has only increased.… Read More