Tag: eda

Advanced Measurements Seminar – Chandler

Advanced Measurements Seminar – Chandler
by Admin on 10-30-2025 at 9:29 am

Join Suren Singh, Application Engineer for Emerging Technologies, and fellow Keysight experts for a hands-on seminar that will help you do what you couldn’t before in RF measurement. Whether you’re looking to advance your expertise or stay ahead of emerging technologies, this hands-on seminar will equip you with the … Read More

Aerospace and Defense Symposium 2025 — El Segundo

Aerospace and Defense Symposium 2025 — El Segundo
by Admin on 10-30-2025 at 9:24 am

Join Chris Johnston, Keysight’s Director of Radar and EW, alongside other Keysight experts, at this year’s Aerospace and Defense Symposium in El Segundo. Gain practical insights, see live demonstrations, and take part in engaging discussions designed to help you stay ahead in our rapidly evolving industry. You’ll walk away… Read More

Webinar: AI/ML Algorithm Design and Testing Toward 6G

Webinar: AI/ML Algorithm Design and Testing Toward 6G
by Admin on 10-30-2025 at 9:18 am

AI and machine learning (AI/ML) are reshaping wireless communications, promising faster, more efficient, and more intelligent networks. But bringing these algorithms into real-world environments isn’t simple — validation and testing remain major hurdles.

In this webinar, industry expert Abhinav Mahadevan shares how

… Read More

Webinar: Insights on Spectrum for 6G

Webinar: Insights on Spectrum for 6G
by Admin on 10-30-2025 at 9:15 am

About this event

Join Roger Nichols, 6G Program Manager, for an insightful discussion on the 6G spectrum. He will cover the current status of 6G technologies, standards, and policies for the next generation of wireless, including developments from 2024 after the World Radio Conference.

Who should attend this event?

This webinar

… Read More

Webinar: Don’t Let VHDL Debugging Slow You Down! Use Questa One Sim

Webinar: Don’t Let VHDL Debugging Slow You Down! Use Questa One Sim
by Admin on 10-29-2025 at 7:18 am

Join us for this essential webinar where we’ll explore how  Questa One Sim empowers VHDL designers to dramatically enhance their debugging productivity. We’ll move beyond basic simulation viewing and dive into advanced features designed to pinpoint issues faster, understand design behavior more intuitively,

… Read More

Webinar: HLV – Formal Verification of Synthesizable C++/SystemC Designs

Webinar: HLV – Formal Verification of Synthesizable C++/SystemC Designs
by Admin on 10-29-2025 at 7:15 am

High-Level Synthesis (HLS) is design flow in which design intent is described at a higher level of abstraction such as SystemC/C++/Matlab/etc. HLS tools are expected to synthesize this code to RTL which can be input to the traditional RTL downstream flow (RTL/GDS).

Formal check tools are difficult to be analyzed on generated

… Read More
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IPLM Today and Tomorrow from Perforce

IPLM Today and Tomorrow from Perforce
by Daniel Nenni on 10-24-2025 at 6:00 am
Categories: EDA, Events, Perforce

ads mdx semiwiki future forward 400x400

Today, Perforce IPLM stands at the intersection of data management, automation, and collaboration, shaping the way companies design the next generation of chips and systems. Looking ahead, its evolution will reflect the growing convergence of hardware, software, and AI-driven engineering.

WEBINAR – Future Forward:… Read More

Webinar: From RTL to Silicon: Qualcomm Closes the Power Gap with Module-Level Insights

Webinar: From RTL to Silicon: Qualcomm Closes the Power Gap with Module-Level Insights
by Admin on 10-15-2025 at 6:01 pm

Traditional RTL low power design techniques such as sequential clock gating are widely deployed across the industry. Yet, even after multiple RTL revisions, residual power inefficiencies often remain undetected until silicon, resulting in missed optimization opportunities.

This seminar presents a refined approach to

… Read More
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Visualizing hidden parasitic effects in advanced IC design 

Visualizing hidden parasitic effects in advanced IC design 
by Admin on 10-15-2025 at 10:00 am
Categories: EDA, Siemens EDA

[white paper] Parasitic Analysis Figures

By Omar Elabd

As semiconductor designs move below 7 nm, parasitic effects—resistance, capacitance and inductance—become major threats to IC performance and reliability, often hiding where netlist reviews cannot reach. Design teams need advanced visualization tools like heat maps, layer-based analysis and direct layout… Read More

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Protect against ESD by ensuring latch-up guard rings

Protect against ESD by ensuring latch-up guard rings
by Admin on 10-13-2025 at 10:00 am
Categories: EDA, Siemens EDA

fig1 latchup event

By Mark Tawfik

Overview: Protecting ICs from costly ESD and latch-up failures

Electrostatic discharge (ESD) events cost the semiconductor industry an estimated $8 billion annually in lost productivity, warranty claims and product failures [1].

Ensuring the robust protection of integrated circuits (ICs) against various… Read More