Badru Agarwala is the CEO and Co-Founder of Rise Design Automation (RDA). With a strong track record of 40 years in EDA, he was previously the General Manager of the Calypto Systems Division at Mentor Graphics, now Siemens EDA. He advanced High-Level Synthesis with Catapult and drove innovations in high-level verification … Read More
William Wang is a world-leading expert in artificial intelligence, specializing in generative AI and large language models. As the Founder, CEO, and Chairman of Alpha Design AI, he brings a wealth of experience from academia and industry, having previously shipped Amazon Q at Amazon AWS Bedrock
A Mellichamp Chair Professor … Read More
In the semiconductor industry High-Level Synthesis (HLS) and SystemC have become essential tools, allowing engineers to model complex hardware designs using familiar C/C++ constructs. Yet, despite the widespread adoption of these languages, the debugging workflows in hardware development lag far behind those in software… Read More
Hello everyone! Welcome to the 2026 DvCon China Conference! As the chair of this conference, l am truly honored to be here with all of you. lt’s exciting to gather together and discuss the latest trends and cutting-edge technologies in the field of design verification.
In recent years, we’ve seen tremendous growth… Read More
Daniel is joined by Dr. Mark Burton, the General Chair for this year’s DVCon Europe. DVCon is the premier conference on the application of languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits.
Mark shares his long history of involvement in DVCon with Dan. He … Read More
DVCon is the premier conference on the application of languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. The focus of the conference is the usage of specialized design and verification languages such as SystemVerilog, Verilog, VHDL, PSS, SystemC and e, as well… Read More
The 2025 Design and Verification Conference (DVCon) was a four-day event packed with insightful discussions, cutting-edge technology showcases, and thought-provoking debates. The conference agenda included a rich mix of tutorial sessions, a keynote presentation, a panel discussion, and an exhibit hall with Electronic… Read More
SystemC version 1.0 came out in 2000 as a C++ class library for system-level modeling and simulation, and on SemiWiki.com there are some 497 references to the language. I wanted to provide an update in this blog so that engineering teams can become more efficient in using SystemC on their SoC projects, saving time and improving product… Read More
Dan is joined by Jakob Engblom this year’s vice chair and keynote chair for DVCon Europe. He’s been in the virtual platforms field since 2002, most recently as director of simulation technology ecosystem at Intel. His interests include simulation technologies, software and hardware testing and validation, programming… Read More
Axiomise pioneered the adoption of formal verification in the semiconductor industry since 2017. Led by visionary CEO, Dr. Ashish Darbari, who has 63 patents in formal verification, and Neil Dunlop an industry veteran with 40 years of experience, Axiomise has helped twenty customers over the last six years by providing them… Read More
