Discuss the performance verification challenges posed by complex SoC with distributed cache from cluster, to interconnect to die-to-die.
12:00 Welcome and Introduction – Mike Bartley, Tessolve
12:00 Nick Heaton, Cadence Design Systems – SoC Verification in a Multi-chip,… Read More
These papers are selected from DVCon and CadenceLive! in 2022 as being most relevant to the DVClub Europe community.
12:00 Welcome and Introduction – Mike Bartley, Tessolve
12:00 Lukas Junger, MachineWare GmbH- SIM-V – Fast, Parallel RISC-V Simulation for Rapid Software Verification… Read More
cocotb is an open source coroutine-based cosimulation testbench environment for verifying VHDL and SystemVerilog RTL using Python. cocotb connects a testbench written in Python with almost all industry-standard… Read More
