IC Designers talk about 28nm to 7nm challenges at #53DAC

IC Designers talk about 28nm to 7nm challenges at #53DAC
by Daniel Payne on 06-20-2016 at 12:00 pm

IC design challenges are different at advanced nodes like 7nm, so to learn more about the topic I attended a panel luncheon at DAC sponsored by Cadence. The moderator was both funny and technically astute, quite the rare combination, so kudos to Professor Rob Rutenbar, a former Neolinear guy now at the University of Illinois. Panelists… Read More


Synopsy Eats Their Own Dogfood

Synopsy Eats Their Own Dogfood
by Paul McLellan on 06-29-2015 at 7:00 am

One of the most interesting presentations that I went to was the last presentation at the Synopsys Custom Lunch (no, the lunch wasn’t custom, we all got the same, but the presentations were about custom design). Since the last presentation was by Synopsys themselves and not by a customer, it wouldn’t seem promising that it could … Read More


Synopsys Vision on Custom Automation with FinFET

Synopsys Vision on Custom Automation with FinFET
by Pawan Fangaria on 06-26-2015 at 7:00 am

In an overwhelmingly digital world, there is a constant cry about the analog design process being slow, not automated, going at its own pace in the same old fashion, and so on. And, the analog world is not happy with the way it’s getting dragged into imperfect automation so it can be more like the digital world. True, the analog world… Read More


Custom Signal Planning Methodologies

Custom Signal Planning Methodologies
by Paul McLellan on 09-20-2011 at 4:08 pm

It is no secret that custom ICs are getting larger and more complex and this has driven chip design teams to split up into smaller teams to handle the manual or semi-automated routing of the many blocks and hierarchical layers that go to make up such a design. These sub-teams don’t just need to handle the routing within their own block(s)… Read More