How to Quickly Optimize BEOL Process at Your Desk?

How to Quickly Optimize BEOL Process at Your Desk?
by Pawan Fangaria on 09-30-2013 at 11:00 am

Engineers are always looking to improve the efficiency of how they work, but don’t want to sacrifice accuracy in the process. This is true in the world of semiconductor process development, where traditional build-and-test cycles are both time and resource intensive. But what if there was a way to do certain steps in a ‘virtual’… Read More


GLOBALFOUNDRIES and Mentor Develop Methods to Identify Critical Features in IC Designs

GLOBALFOUNDRIES and Mentor Develop Methods to Identify Critical Features in IC Designs
by glforte on 11-28-2012 at 3:00 pm

Since the beginning of the semiconductor industry, improving the rate of yield learning has been a critical factor in the success silicon manufacturing. Each fab has dedicated yield teams that look at the yield of wafers manufactured the previous day and attempt to find the root cause of any unexpected “excursions.” In earlier… Read More