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Crack the Verification Double Trouble!
Register for CadenceTECHTALK to find out how to achieve verification closure with the same coverage with up to a 10X reduction in simulation cycles.
Chips are becoming bigger and more complex, adding to already existing verification woes. Design and verification engineers struggle with… Read More
Register for CadenceTECHTALK to find out how to achieve verification closure with the same coverage with up to a 10X reduction in simulation cycles.
Chips are becoming bigger and more complex, adding to already existing verification woes. Design and verification engineers struggle with running billions of regression cycles… Read More
Date: Thursday, September 29, 2022
Time: 09:00 BST / 10:00 CEST / 11:00 EEST and Israel
Crack the Verification Double Trouble! Chips are becoming bigger and more complex, adding to already existing verification woes. Design and verification engineers struggle with running billions of regression cycles to achieve the desired
…
Read More
Paul Cunningham, CVP and GM of the System Verification Group at Cadence gave the afternoon Keynote on Tuesday at DVCon and doubled down on his verification-throughput message. At the end of the day, what matters most to us in verification is the number of bugs found and fixed per dollar per day. You can’t really argue with that message.… Read More
