PVT and Statistical Design in Nanometer Process Geometries

PVT and Statistical Design in Nanometer Process Geometries
by Daniel Nenni on 09-18-2011 at 9:00 am

On Sept 22, 2011, the nm Circuit Verification Forumwill be held in Silicon Valley, hosted by Berkeley Design Automation. At this forum, Trent McConaghy of Solido DA will present a case study on the TSMC Reference Flow 2.0 VCO circuit, to showcase Fast PVT in the steps of extracting PVT corners, verifying PVT, and doing post-layout… Read More