The increasing demands of data-intensive applications necessitate more efficient storage and memory utilization. The rapid evolution of AI workloads, particularly with Generative AI (GenAI), demands infrastructure that can adapt to diverse computational needs. AI models vary widely in resource requirements, necessitating… Read More
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Navigating the 1.6Tbps Era: Electro-Optical Interconnects and 224G Links
In the relentless pursuit of ever-increasing data speeds, the 1.6 Terabits per second (Tbps) era looms on the horizon, promising unprecedented levels of connectivity and bandwidth within data centers. As data-intensive applications proliferate and the demand for real-time processing escalates, the need for robust and efficient… Read More
Mitigating the Effects of DFE Error Propagation on High-Speed SerDes Links
As digital transmission speeds increase, designers use various techniques to improve the signal-to-noise ratio at the receiver output. One such technique is the Decision Feedback Equalizer (DFE) scheme, commonly used in high-speed Serializer-Deserializer (SerDes) circuits to mitigate the effects of channel noise and … Read More
Don’t Blame Trump for Auto Downturn
There is a temptation to blame U.S. President Donald J. Trump for everything that is right or for everything that is wrong in the world today. Either that or blame Brexit. It’s just possible that Uber, instead, ought to be considered the target of shame for everything from traffic fatalities to global warming.
The automotive… Read More
SRAM Optimization Saves Power on SOC’s and in Systems
Mobile device designers face the dilemma of reducing power and at the same time maintaining or increasing performance. Consumers will not tolerate increased battery life at the expense of performance. If it were otherwise, designers could simply dial back clock rates. Without this simple cure, the best way to reduce power for… Read More