Constraints-Driven CDC and RDC Verification Including UPF Aware Analysis
Synopsys Webinar | Thursday, June 23, 2022 | 10:00 – 11:00 a.m. Pacific
Today’s million gates integrated circuits (ICs) involve various intellectual properties (IPs) interfacing with each other through multiple asynchronous clock and reset domains. Ensuring all clocks propagate concurrently across each clock tree