AMS Verification and Regression Testing of SoC Designs

AMS Verification and Regression Testing of SoC Designs
by Daniel Payne on 03-25-2014 at 10:02 am

Digital verification engineers on SoC designs have adopted many techniques to help ensure first silicon success: using compiled simulators, constrained random test, simulation farms, SystemVerilog methodology, and self-checking testbenches. AMS verification has tended to be ad-hoc or sharply divided into separate analog… Read More