On the high-speed digital design frontier with Keysight’s Hee-Soo Lee

On the high-speed digital design frontier with Keysight’s Hee-Soo Lee
by Don Dingee on 02-16-2026 at 10:00 am

Chiplet 3D Interconnect Designer reduces interconnect analysis in high-speed digital design from weeks to minutes

High-speed digital (HSD) design is one of the more exciting areas in EDA right now, with design practices, tools, and workflows evolving to keep pace with increasing design complexity. With the annual Chiplet Summit and DesignCon festivities right around the corner, we sat down with Keysight’s Hee-Soo Lee, HSD Segment Lead, … Read More


Analyzing All of those IC Parasitic Extraction Results

Analyzing All of those IC Parasitic Extraction Results
by Daniel Payne on 03-30-2017 at 12:00 pm

Back at DAC in 2011 I first started to hear about this EDA company named edXact that specialized in reducing and analyzing IC parasitic extraction results. So Silvaco acquired edXact and I wanted to get an update on what is new with their EDA tools that help help you to analyze and manage the massive amount of extracted RLC and even K … Read More