Webinar DFT 2025 banner mar11 (1)
Semiconductor Expert Forum

Podcast EP187: The Drivers and Dynamics of the Worldwide Semiconductor Supply Chain with Sypplyframe’s Richard Barnett

Podcast EP187: The Drivers and Dynamics of the Worldwide Semiconductor Supply Chain with Sypplyframe’s Richard Barnett
by Daniel Nenni on 10-13-2023 at 10:00 am

Dan is joined by Richard Barnett, chief marketing officer and SaaS sales leader at Supplyframe. With more than 25 years of leadership experience in strategic marketing, sales and product management, Richard is recognized as a thought leader on supply chain and strategic sourcing transformation as well as digital marketing … Read More

Posted on

CEO Interview: Islam Nashaat of Master Micro

CEO Interview: Islam Nashaat of Master Micro
by Daniel Nenni on 10-13-2023 at 6:00 am
Categories: CEO Interviews

Islam Nashaat

Eng. Islam Nashaat received his B.Sc. and M.Sc. degrees from Ain Shams University, Cairo, Egypt, in 2010 and 2017, respectively. He joined Si-Vision as an Analog Physical Design Engineer in 2010, where he initiated the company’s CAD team in 2013, and became CAD and Physical Design Team Lead in 2016 after the company’s flagship … Read More

Posted on

TSMC N3E is ready for designs, thanks to IP from Synopsys

TSMC N3E is ready for designs, thanks to IP from Synopsys
by Daniel Payne on 10-12-2023 at 10:00 am
Categories: Foundries, IP, Synopsys, TSMC

synopsys ucie phy ip min

TSMC has been offering foundry services since 1987, and their first 3nm node was called N3 and debuted in 2022; now they have an enhanced 3nm node dubbed N3E that has launched.  Every new node then requires IP that is carefully designed, characterized and validated in silicon to ensure that the IP specifications are being met and … Read More

Posted on

Synopsys Panel Updates on the State of Multi-Die Systems

Synopsys Panel Updates on the State of Multi-Die Systems
by Bernard Murphy on 10-12-2023 at 6:00 am
Categories: AI, Chiplet, EDA, Synopsys

multi die 525x315 light

Synopsys recently hosted a cross-industry panel on the state of multi-die systems which I found interesting not least for its relevance to the rapid acceleration in AI-centric hardware. More on that below. Panelists, all with significant roles in multi-die systems, were Shekhar Kapoor (Senior Director of Product Management,… Read More

Posted on

Placement and Clocks for HPC

Placement and Clocks for HPC
by Paul McLellan on 10-11-2023 at 10:00 am
Categories: EDA, Siemens EDA

cts

You are probably familiar with the acronym PPA, which stands for Power/Performance/Area. Sometimes it is PPAC, where C is for cost, since there is more to cost than just area. For example, did you know that adding an additional metal layer to a chip dramatically increases the cost, sometimes by millions of dollars? It requires a … Read More

Posted on

Long-standing Roadblock to Viable L4/L5 Autonomous Driving and Generative AI Inference at the Edge

Long-standing Roadblock to Viable L4/L5 Autonomous Driving and Generative AI Inference at the Edge
by Lauro Rizzatti on 10-11-2023 at 6:00 am
Categories: AI, Automotive

Table I

Two recent software-based algorithmic technologies –– autonomous driving (ADAS/AD) and generative AI (GenAI) –– are keeping the semiconductor engineering community up at night.

While ADAS at Level 2 and Level 3 are on track, AD at Levels 4 and 5 are far from reality, causing a drop in venture capital enthusiasm and money. Today,… Read More

Posted on

Synopsys – TSMC Collaboration Unleashes Innovation for TSMC OIP Ecosystem

Synopsys – TSMC Collaboration Unleashes Innovation for TSMC OIP Ecosystem
by Kalar Rajendiran on 10-10-2023 at 10:00 am
Categories: AI, Automotive, EDA, Foundries, IP, Synopsys

L.C. OIP 2023

As the focal point of the TSMC OIP ecosystem, TSMC has been driving important initiatives over the last few years to bring multi-die systems to the mainstream. As the world is moving quickly toward Generative AI technology and AI-based systems, multi-die and chiplet-based implementations are becoming essential. TSMC recently… Read More

Posted on

Disaggregated Systems: Enabling Computing with UCIe Interconnect and Chiplets-Based Design

Disaggregated Systems: Enabling Computing with UCIe Interconnect and Chiplets-Based Design
by Kalar Rajendiran on 10-10-2023 at 6:00 am
Categories: Alphawave Semi, Chiplet, IP

AresCORE UCIe PHY Support for All Package Types

The world of computing is evolving rapidly, with a constant demand for more powerful and efficient systems. Generative AI has driven exponential growth in the amount of data that is generated and processed at very high data speeds and very low latencies. Traditionally, computing systems have been built using monolithic designs,… Read More

Posted on

Can Generative AI Recharge Phone Markets?

Can Generative AI Recharge Phone Markets?
by Bernard Murphy on 10-09-2023 at 10:00 am
Categories: AI, Mobile

Consensus on smartphone markets hovers somewhere between slight decline and slight growth indicating lack of obvious drivers for more robust growth. As a business opportunity this unappealing state is somewhat offset by sheer volume ($500B in 2023 according to one source) but we’re already close to peak adoption outside of … Read More

Posted on

SPIE- EUV & Photomask conference- Anticipating High NA- Mask Size Matters- China

SPIE- EUV & Photomask conference- Anticipating High NA- Mask Size Matters- China
by Robert Maire on 10-09-2023 at 6:00 am
Categories: Chiplet, Events, Lithography, Semiconductor Advisors, Semiconductor Services

Conference EUV Lithography

– SPIE EUV & Photomask conference well attended with great talks
– Chip industry focused on next gen High NA EUV & what it impacts
– Do big chips=big masks? Another Actinic tool?
– AI & chip tools, a game changer- China pre-empting more sanctions

The SPIE EUV & Photomask conference in Monterey
… Read More