I will see you at the Substrate Vision Summit in Santa ClaraWIth packaging being one of the top sources…Read More
The Immensity of Software Development and the Challenges of Debugging Series (Part 4 of 4)The Impact of AI on Software and Hardware…Read More
Alchip is Paving the Way to Future 3D Design InnovationAt the recent TSMC OIP Ecosystem Forum in…Read More
Maheen Hamid, a member of the ESD Alliance (a SEMI Technology Community) Governing Council and a member of SEMI’s North America Advisory Board, is an astute business executive. Together with her husband Adnan Hamid, they founded Breker Verification Systems, a company developing test synthesis solutions. She serves today … Read More
We all know chip design is changing in substantial ways and at a fast pace. The demands being placed on semiconductor systems are growing dramatically, and the innovation being delivered to address those demands is just as dramatic. Everyone seems to have an opinion on these trends, and a set of predications to make sense out of it… Read More
Cadence hosted a panel at DAC on how EDA, MCAD and industrial software have come together, a topic I always find interesting. Many years ago, I worked on a NAVAIR contract bid team, an eye-opener for a young engineer who thought that innovation started and ended with electronic design. I remember CATIA (3D modeling) being a component… Read More
The opening day at DAC was Monday and I had an appointment with Simon Rance (Cliosoft) and Stephen Slater, Product Manager of Keysight EDA in their suite. Back in February Daniel Nenni wrote about Keysight EDA acquiring Cliosoft, adding design data and IP management to their software offerings. I really wanted to hear how that … Read More
In the assessment of wafer lithography processes, normalized image log-slope (NILS) gives the % change in width for a given % change in dose [1,2]. A nominal NILS value of 2 indicates 10% change in linewidth for 10% change in dose; the % change in linewidth is inversely proportional to the NILS. In a previous article [2], it was shown… Read More
The trend is undeniable. Highly integrated monolithic chips can no longer handle the demands of next-generation systems. The reasons for this significant shift in design are many. Much has been written on the topic; you can get a good overview of the forces at play in multi-die design here. These changes represent the next chapter… Read More
Dan is joined by Dave Lazovsky, CEO of Celestial AI. Dave has an in-depth knowledge of semiconductor, data/telecommunications, photonics and clean energy industries, as well as extensive international business experience. He currently has over 50 issued and 5 pending U.S. patents.
In this broad and forward-looking discussion,… Read More
-ASML reports better results & guide despite China restrictions
-Supports our view of China issues not that impactful longer term
-Industry recovery seems very far off with more delays
-ASML remains the best, most robust story in a weak industry
ASML reported revenues of Euro6.9B… Read More
My recent article, ‘Chip War without Soldiers’ explained the importance of upskilling and preparing the chip design workforce in this current scenario, and it also explained how it will lead to ‘Fabs without Chips’ if we don’t prioritize it. VLSI Engineers are the pillars of the semiconductor industry, and they can only transform… Read More
Last week, Efabless announced the second edition of its AI Generated Open-Source Silicon Design Challenge series. As we discussed in earlier blogs, the first challenge was a great success with twelve submissions and six successful designs created in just three weeks. The contestants used natural language prompts to create… Read More
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