Staff Engineer, Physical Design

Primary Responsibilities:

The employee is responsible for the complete physical design of multiple large and complex ASIC and FPGA blocks, and may also contribute to full chip design and integration for Achronix’s FPGA products. The employee is expected to take independent ownership of reasonably complex design challenges, which may include:

• Floorplanning, place, and route as well as CTS using physical design tools
• Physical verification
• Physical integration
• Physical design methodology
• STA

The employee is also expected to participate in methodology development activities.

Skills:

• Expertise in physical design activities: Floorplanning, CTS, P&R
• Expertise in physical verification
• Expertise with physical design and verification tools
• A strong understanding of layout DRC rules and concepts as well as device identification concepts
• Strong programming knowledge in Perl, TCL, and/or Shell Scripting
• Strong communication skills
• Ability to work in a dynamic and fast-paced environment with a proactive mindset
• Experience in 16nm and smaller process nodes is a plus
• Experience in custom layout is a plus
• Working knowledge of ICC2 and ICV is a plus

Experience/Education:

• Preferred BS/MS and 6-12 years of experience in physical design
• Previous experience in 2-3 VLSI projects in deep submicron technologies