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The team is responsible for integrating the company IP cores into FPGA-based emulation environments as well as to develop new emulation features, providing the company with state of the art emulation capabilities, enabling it to demonstrate the full potential of the IPs being developed. Given the complexity of the task in hand, this work requires skilled FPGA engineers with experience in designing and mapping logical resources in very large devices, achieving the target timing margins while attaining optimal device usage. Alongside, these tasks require close collaboration with other company groups, including software and firmware teams, who make extensive use of these emulation platforms.
Responsibilities:
Integrate RTL code releases into new FPGA designs;
Configure FPGA peripherals for maximizing the performance of the RISC-V prototyping solutions;
Implement new RTL modules to provide the RISC-V core under emulation/prototyping with the optimal I/O configurations;
Interact with other teams to understand their requirements for new features and on how that can be leveraged into the FPGA designs;
Maintain and further improve our in-house FPGA resource pool;
Provide support and develop new features to be used in demonstration systems for company clients.
Requirements
+7 years of industrial experience
Bachelor’s, Master or PhD degree in Computer Science, Electronics, Telecommunications or equivalent.
Essential Knowledge:
Experience working with Xilinx (or Altera) FPGAs using Xilinx Vivado (or Altera Quartus).
Experience in using FPGA Integrated Logic Analyser probes;
Knowledge of AXI4/AXI4-Lite, UART, I2C, SPI protocols;
Proficient with HDL languages such as Verilog/SystemVerilog (or VHDL);
Experienced with FPGA timing and placement constraints using SDC syntax;
Experienced in TCL and Bash scripting for FPGA;
Experienced with GIT file version control;
Experienced with Linux based operating systems / distributions;
Knowledge of C/C++ and Python;
Valued Knowledge:
Experience in packing IPs and integrating different IPs into Xilinx BlockDesigns;
Development of RTL test benches and simulation tools such as Siemens ModelSim/QuestaSim;
Experience with high-end FPGAs such Xilinx Virtex Ultrascale and Ultrascale Plus;
Knowledge on Xilinx Aurora, PCIe and Ethernet protocols;
Knowledge of CHI protocol;
Experience in hardware debugging, using laboratory equipment such as multimeter, oscilloscopes, waveform generators, spectrum analysers, etc.
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