Senior DFT Design Engineer

Job Description:

We are seeking a senior skilled DFT Design Engineer to develop and implement comprehensive Design for Test solutions across our semiconductor products. This role involves RTL design, verification, and manufacturing support for various DFx methodologies including SCAN, MBIST, and BSCAN implementations. We are seeking a highly skilled DFT Design Engineer to join our semiconductor engineering team and drive the development of cutting-edge Design for Test solutions across our product portfolio. This critical role combines deep technical expertise in digital design with specialized knowledge of test methodologies to ensure our silicon products meet the highest quality standards for high-volume manufacturing.

As a Senior DFT Design Engineer, you will be responsible for architecting, implementing, and optimizing comprehensive test strategies that span from initial RTL development through production manufacturing. You will work at the intersection of design and test, collaborating with cross-functional teams including architecture, verification, physical design, and manufacturing to deliver robust DFT solutions that enable efficient testing while meeting stringent power, performance, and area requirements. The successful candidate will have extensive experience in DFT methodologies and will play a pivotal role in defining test architectures for complex SoCs, developing innovative solutions to challenging testability problems, and ensuring seamless integration of DFT features across multiple design hierarchies.

This position offers the opportunity to work on industry-leading semiconductor products and contribute to the advancement of DFT technologies in next-generation computing platforms. This role involves RTL design, verification, and manufacturing support for various DFx methodologies including SCAN, MBIST, and BSCAN implementations, with a focus on achieving optimal test coverage, minimizing defect escape rates, and reducing overall test costs while maintaining design integrity and performance targets.

Key Responsibilities

Design & Development:

• Develops logic design, register transfer level (RTL) coding, and simulation for DFT implementations
• Provides DFT timing closure support and generates test content for manufacturing delivery
• Implements various DFx content including SCAN, MBIST, and BSCAN methodologies
• Applies strategies, tools, and methods to write and generate RTL and structural code for DFT integration

Architecture & Collaboration:

• Participates in defining architecture and microarchitecture features for blocks, subsystems, and SoCs
• Collaborates on DFT design including TAP, SCAN, MBIST, BSCAN, processor monitors, and in-system test/BIST
• Integrates DFT blocks into functional IP and SoC while supporting customer integration requirements

Optimization & Verification:

• Optimizes logic design to meet power, performance, area, timing, test coverage, DPM, and test time/vector memory reduction goals
• Reviews verification plans and drives DFT design verification to achieve architecture specifications
• Ensures design features are verified correctly and implements corrective measures for failing RTL tests

Manufacturing & Production Support:

• Develops HVM (High Volume Manufacturing) content for rapid bring-up and production ramp on ATE (Automatic Test Equipment)
• Collaborates with post-silicon and manufacturing teams for silicon verification and debug support
• Drives high test coverage through structural and IP-specific tests to achieve quality and DPM objectives
• Documents learnings and improvement requirements for design and validation processes

Intel is in the process of securing office space in Fort Collins, Colorado, which will serve as your assigned work location in the future. Once the site is operational, your position will follow Intel’s hybrid work model, which currently requires on-site presence at least four days per week. Until the office is ready, you will be classified as a remote employee. 

Qualifications:

Minimum Qualifications

Education & Experience:

• Bachelor’s degree in Electrical Engineering, Computer Science, or related field with 4+ years of industry experience or Master’s degree in Electrical Engineering, Computer Science, or related field with 3+ years of industry experience

Technical Requirements:

• 5+ years of hands-on experience with DFT (Design for Test) methodologies
• 5+ years of experience with Array Test including MBIST (Memory Built-In Self-Test)
• Experience in RTL coding, simulation, and verification
• Experience in semiconductor manufacturing test processes and ATE systems

Preferred Qualifications

• Expert-level proficiency in Tessent DFT tool suite
• Advanced expertise in PrimeTime, specifically with DFT constraints and timing analysis
• Experience with additional DFT tools and methodologies
• Knowledge of advanced test compression techniques and fault models
• Experience with SoC-level DFT integration and customer support
• Background in post-silicon validation and debug
• Familiarity with industry test standards and protocols
• Experience in test cost optimization and DPM improvement initiatives