Senior or Lead DDR Engineer

Description

Are you passionate about microprocessor architecture? We need you! As a Senior Memory Design Engineer, you play a crucial role in designing and developing memory subsystem solutions for our semiconductor portfolio. You will work within the Memory Design Team and work closely with other teams’ highly skilled engineers to create efficient and high-performance memory subsystems that are essential for modern designs.

What do we offer? Flexible work schedules, competitive pay, a highly learning environment, and opportunities for advancement. Come and join us in the beautiful city of Barcelona!. Candies, coffee and free spanish lessons included!. (Visa sponsorship if required)

Requirements

Required: 

• Industrial experience +8 years
• Knowledge of DDR or HBM memories. Proven experience in design and/or integration of memory controllers.
• Experience in AXI protocol.
• Proficiency in RTL design using Verilog or VHDL
• Experience with Timing and Timings Constraints
• Experience with basic block level testing

Desired: 

• Master or PhD
• Knowledge of scripting languages (Python, Perl, Bash, TCL).
• Knowledge of revision control methodology and tools (git, svn).
• Knowledge of coherency concepts and protocols.
• Experience in memory map definition.