R&D Engineering, Staff Engineer

Domain:

* We, at Systems Design Group, Synopsys, are expanding our R&D team, involved in creating industry-leading System verification solutions.

* Our market-leading product solutions target High Performance Computing, Data Centre, Mobile/Client, Automotive and IoT segments.

* As an R&D Engineer, you will get an opportunity to join our team of Verification experts involved in developing solutions around system verification, including but not limited to on-chip, chi-to-chip, die-to-die, coherent and non-coherent design topologies.

Responsibilities:

* You will be involved in creating System verification solutions for Arm AMBA5 protocols such as CHI, AXI5/ACE5 for on-chip, chi-to-chip, die-to-die, coherent and non-coherent design topologies.

* You will be responsible for functional verification involving coherent and non-coherent IP designs.

* You will be working with market makers in High Performance Computing, Data Centre, Mobile/Client, Automotive and IOT segments, to define & create products to meet their complex verification requirements.

Qualification & Experience:

* B.E/B.Tech in Electrical engineering/Electronics & Communications Engineering with 5 to 8 years of relevant experience, OR

* M.E/M.Tech in VLSI Design/Microelectronics with 3 to 6 years of relevant experience

* Good academic track record from reputed institutes

Location:

Bengaluru, KA, India
Fulltime employment, Work from Office

Skills:

* Hands-on working experience in architecting & building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, Verification Ips.

* Hands-on working experience in creating verification plans, functional coverage-driven verification closure of real designs.

* Hands-on working experience and in-depth understanding of Cache coherency protocols such as Arm AMBA AXI/ACE, CHI; CCIX or CXL.Cache.

* Hands-on working experience in verifying Interconnect/NOC designs is an added advantage.

* Background of Verification IP development, Test suites in SystemVerilog UVM for industry-standard interface/bus protocols is an added advantage.

* Excellent problem-solving skills, debugging and analytical skills are a must.

* Expertise in Object-oriented programming concepts and excellent programming skills are a must.

* Familiarity with version control systems such as Perforce is expected.

* Hands-on experience in writing scripts using Perl/Python/Shell scripting is expected.

* Creativity & innovation mindset is expected.

* Excellent verbal & written communication skills are a must.

* Good team player.

* Passion for Functional Verification.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.