Principal Design Engineer
Website Cadence
- S degree with 10+ years of applicable experience, MS degree with 7+ years of applicable experience in electrical engineering, microelectronics.
- Experienced with ASIC design flow, hierarchical physical design strategies, and methodologies and understand deep sub-micron technology issues.
- Solid knowledge on LP Design, static timing analysis, EM/IR-Drop/crosstalk analysis, physical verification, DFM.
- Successful track records of taping out complex, 16nm/10nm/7nm chips.
- Automation and programming-minded, solid coding experience in Makefile/Tcl/Tk/Perl.
- Self-motivated, able to work independently or as a team player, excellent verbal and written communication skills in English.
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To view the job application please visit cadence.wd1.myworkdayjobs.com.
Intel to Compete with Broadcom and Marvell in the Lucrative ASIC Business