Lead Verification Engineer

Overview

This is an opportunity to join a dynamic and growing team of experienced engineers developing high-performance physical IP for industry-standard protocols.

The successful candidate will be a highly motivated self-starter who is able to work independently to complete assigned tasks within required project timelines with high quality.

The candidate will primarily be responsible for the verification of digital RTL and development of re-usable verification components and environments.

It is also expected that the candidate will contribute to all aspects of digital verification including flow development, test plan development and execution, functional coverage closure, and code coverage closure.

The ideal candidate will have a fundamental understanding of the end-to-end verification flow in order to accurately and efficiently communicate with all members of the technical staff regarding overall project development progress and status.

The most successful candidates will be able to demonstrate excellent command of fundamental logic principles as well as excellent problem solving and communication skills.

The candidate should be able to work as part of a small and focused team of engineers and be able to collaborate successfully as needed with design teams, verification teams, project management, and digital and analog design teams in multiple worldwide geographies.

The Candidate should be willing to work full time in the Montreal, Quebec, Canada office and be willing to travel as required by job function (expectation is 5% travel or less).

Design IP is growing organization within Cadence and our complete IP portfolio can be found here http://ip.cadence.com/ipportfolio/ip-portfolio-overview.

Minimum Experience:

• Bachelor of Science in Electrical(EE)/Computer Engineering (CPE) or Computer Science (CSC)
• Understanding of verification architecture and methodologies
• Understanding of Metric Driven Verification
• Understanding of Universal Verification Methodologies
• Understanding of the identification, planning and creation of functional coverage and checks
• Understanding of System Verilog Assertions (SVAs)
• Understanding of digital design flow

Preferred Experience:

• Master of Science in EE/CPE/CSC
• Experience with SystemVerilog UVM coding language is desired
• Experience with scripting languages such as Python, Perl, Ruby, Sed, or Awk is also strongly preferred
• Exposure to Standard Protocol knowledge for any of the following areas: PCIe, USB, SATA, Ethernet, Display Port, HDMI
• Exposure to Formal Verification Technologies
• Exposure to Mixed Signal Design experience
• Experience with Cadence tools experience
• Exposure to Low Power verification experience using CPF or UPF