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Coming up with newer versions of on-chip transfer protocols aimed for high speed on hyperflex and eASIC architectures
Developing new interconnect topologies to maximize data transfer throughput over long distances over FPGAs
Extending support for AXI and other Industry Standard Memory Mapped and Streaming protocols
Developing robust IP and networks which customers use in mission critical debug environments
Developing microprocessor and microcontroller architectures optimized for implementation on Intel FPGAs
Experience in technical leadership roles in Soft IP Design Solutions for ASIC/FPGA.
Excellent verbal and written communication skills Working knowledge of hardware and software tools for content creation, execution and debug
Strong attention to technical detail, data analysis and situational problem-solving skills
Ability to handle complex issues with clarity to drive decisions Self-motivated and willing to take additional responsibilities for team’s success Multitasking skills Collaborative, inclusive, influencer
Speculative Execution: Rethinking the Approach to CPU Scheduling