Formal verification engineer student
Your mission
- 10h/week, from July 2025, hybrid
- Be trained in state-of-the-art formal verification techniques
- Be part of our verification team and help us verifying customers designs
- Work on your own, with a team or lead your own project
Your profile
- Ability to work independently and in a team
- Basic knowledge in SystemVerilog/VHDL
- Business level English
- Beneficial: basic knowledge in SVA
Why us?
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Flexible working hours that allow you to be the boss of your own work
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Contribute your own ideas and manage your own development
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Remote and on-site work
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Regular team events in a young, dynamic, intercultural team
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Hands-on insight into the working world and the growth of a startup
About us
At LUBIS EDA, we help our customers to find simulation-resistant bugs in their high-risk IP blocks. There is a large demand for formal methods, as it is a very efficient way to tackle the industry’s verification problems. We developed a game-changing software solution that we use inhouse, making Formal Verification more intuitive and easier. We are looking for people that want to become an expert in their field. Make a change and built a company together with us!
Apply for job
To view the job application please visit lubis-eda.jobs.personio.de.
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