Digital Verification Engineer

Description

About the Business Unit:

The Vision Business Unit (VBU) at Ceva combines a dynamic startup environment with a stable, well-positioned IP company.

About the Role:

As a Digital Verification Engineer, you will work on a full state of the art verification flow from architecture definition, through verification strategy, environment micro-ARCH, test plan, functional coverage plan and up to advanced verification sign off process

Responsibilities:

You will directly contribute to the verification of our fully integrated solutions, design in System Verilog new verification environment checker and test bench, being a major contributor to the verification process, and improve the performance and quality.

Requirements

• B.Sc /M.Sc. graduates in Electrical Engineering from a leading University.
• 2-6 years of experience in Verification.
• Knowledge of SV-UVM, Specman and C++.
• Self-motivated and self-directed, proactive.
• Ability to achieve results in a fast moving, agile flow and dynamic environment, both locally and across the organization.
• Ability to troubleshoot and analyze complex problems.
• Great communication skills.
• Fluent English.
• Team player.