Founding EDA R&D Engineer: Reconfigurable Compute Acceleration

DSV is a venture builder and new paradigm for applied science. We’re building an entirely new paradigm for computation that has the software level reconfiguration of FPGAs whilst being several orders of magnitude faster than ASICs and other hardware accelerators. The company is currently in stealth and we’re looking for the final member of the founding team.

The ideal candidate would be passionate about high performance automation across VLSI architecture, logic, and physical design, with a particularly creative attitude, deep insight on one or two areas below with an demonstrated ability to break new ground and a desire to join an early stage startup.

• Experience with, and ideally in developing, placement and routing (PNR) or other ECAD/EDA tools and ideally in developing the underlying algorithms.
• Experience in logic synthesis, RTL, verification and power estimation with a particular focus on performance models for analysing microarchitecture trade-offs and static timing analysis, timing libraries and clock tree synthesis (CTS)
• Experience in physics based simulation, geometry modelling and simulation of GPU or CPU architectures and / or parallel programming.
• Ability to think across the stack and layers of abstraction with a strong view on areas that are open to optimisation.
• A broad interest in non-volatile memory would also be a bonus

More information about how we build companies and what we’re working on at the application link.

Or feel free to drop a CV over to mark@dsv.io