Clocking Design Engineer

Job Description:

We are seeking a highly skilled Clocking Design Engineer to join our dynamic team.

You will be part of the clock team supporting Intel’s flagship CPU designs in the most advanced process nodes. In this role, you will be involved in clocking architecture definition, design and implementation of custom clock global network, development of clock tree synthesis flow, as well as custom clock circuit design and clock library cell design.

This is a cross-functional role that requires interfacing and collaborating with other teams such as architecture, physical design, full chip integration, RTL, circuits, validation, design automation team and EDA vendors, in a high-paced atmosphere.

Key Responsibilities:

• Implement custom clock distribution network for high frequency flagship CPU designs
• Develop clock tree synthesis flow and deliver custom clock solutions for high frequency flagship CPU designs
• Design custom circuits and library cells related to clock distribution

Qualifications:

You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• Bachelor´s degree in electrical engineering, computer engineering related STEM field and 4+ years of experience and/or Master´s degree and 3+ years of experience and/or PhD and 2+ years of experience, ​during which the candidate has demonstrated experience in:
  • Physical design and advanced process technologies and circuit implementation
  • Static timing analysis, clock tree synthesis, and clock-related timing parameters
  • Use of industry-standard scripting and automation within EDA tool flows

Preferred Qualifications:

• 3+ years of experience in:
  • Backend design and/or integration on leading edge process nodes
  • High frequency clock distribution design and implementation, custom circuits and clock tree synthesis