Array
(
[content] =>
[params] => Array
(
[0] => /forum/whats-new/latest-activity?before_id=96824
)
[addOns] => Array
(
[DL6/MLTP] => 13
[Hampel/TimeZoneDebug] => 1000070
[SV/ChangePostDate] => 2010200
[SemiWiki/Newsletter] => 1000010
[SemiWiki/WPMenu] => 1000010
[SemiWiki/XPressExtend] => 1000010
[ThemeHouse/XLink] => 1000970
[ThemeHouse/XPress] => 1010570
[XF] => 2030770
[XFI] => 1060170
)
[wordpress] => /var/www/html
)
You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please,
join our community today !
JavaScript is disabled. For a better experience, please enable JavaScript in your browser before proceeding.
You are using an out of date browser. It may not display this or other websites correctly.
You should upgrade or use an
alternative browser .
D
TSMC N6 and TSMC N5 came out at the same time (Q1 2020). TSMC considers N7, N7+ and N6 one node, that is how they report it. Same with...
Sep 29, 2025
D
From Wikichip N3B is ouch too many layers and info on how many layers Intel uses EVU from what i know on Intel 4 the EUV use is pretty...
Sep 29, 2025
D
From my notes:
TSMC N7 is DUV, TSMC N7+ uses 4 EUV layers, TSMC N6 uses 5 EUV layers, TSMC N5 uses 14 EUV layers.
AMD and HiSilicon...
Sep 29, 2025
D
N7 was all-DUV, N7P had some EUV layers but incompatible design rules so no IP porting. IIRC (we didn't use it) N6 was a shrunk N7 (with...
Sep 29, 2025
I actually laughed out loud on this one. I am not a regular Barron's reader but I had thought highly of them.
Here is the authors bio...
Sep 29, 2025
B
Yes, N3B is 25 EUV layers and N3E is 19. TSMC calls it yield learning.
Intel 4...
Sep 29, 2025
B
1c uses EUV as well:
AI overview:
SK hynix:
This company is a leader in EUV adoption for DRAM, utilizing five or more EUV layers for...
Sep 29, 2025
B
When I looked at the chart for ASML, I think Barrons is wrong, you'd be happy to own ASML and enjoy the tailwind of a weaker dollar on...
Sep 29, 2025
TSMC N6 and TSMC N5 came out at the same time (Q1 2020). TSMC considers N7, N7+ and N6 one node, that is how they report it. Same with...
Sep 29, 2025
S
I can bet someone must be planning in WH to reduce this reliance but how successful will that be only time can tell.
Sep 29, 2025
S
And then they have to chose: to die or to find ways to work with TSM in TW.
Sep 29, 2025
P
And then they have to chose: to die or to find ways to work with TSM in TW.
Sep 29, 2025
S
OK, my first speculation was wrong then (but my second one wasn't!) -- note the comment about backward-compatible design rules which was...
Sep 29, 2025
OK, my first speculation was wrong then (but my second one wasn't!) -- note the comment about backward-compatible design rules which was...
Sep 29, 2025
I
OK, my first speculation was wrong then (but my second one wasn't!) -- note the comment about backward-compatible design rules which was...
Sep 29, 2025
Like.
TSMC N6 and TSMC N5 came out at the same time (Q1 2020). TSMC considers N7, N7+ and N6 one node, that is how they report it. Same with...
Daniel Nenni replied to the thread ASML Builds Machines that Make AI Chips. Why It’s Missing Out on the Boom..I actually laughed out loud on this one. I am not a regular Barron's reader but I had thought highly of them. Here is the authors bio...