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Yes I am sure. Would you dare to question Scotten Jones? ;)
From TSMC:
EUV process improves logic density; provides backward...
Sep 29, 2025
S
i was seeing rumors that N3 and N2 had the same EUV layers count and those seemed false thanks for the confirmation :) as for N2 expense...
Sep 29, 2025
S
If you think N3 was bad for EUV layers (and wafer prices!), you shouldn't even look at N2... ;-)
Sep 29, 2025
I
If you think N3 was bad for EUV layers (and wafer prices!), you shouldn't even look at N2... ;-)
Sep 29, 2025
I
Are you absolutely sure about N6? As I said we never used it, but I'm pretty sure it was a linear shrink and cost reduction of N7, not...
Sep 29, 2025
I
I should hope I was right, what I said was based on actual PDK and layouts, not TSMC (or any other) website... ;-)
Sep 29, 2025
They can do it exactly because of that: half of US stock market will be taking a hit to the face in case of anything dramatic
Sep 29, 2025
S
Well considering Nvidia/Apple/Google's/AWS/AMD/QCOM reliance yup but TSMC will suffer setback as well. No one will win neither...
Sep 29, 2025
S
Yes, N3B is 25 EUV layers and N3E is 19. TSMC calls it yield learning.
Intel 4...
Sep 29, 2025
Yes, N3B is 25 EUV layers and N3E is 19. TSMC calls it yield learning.
Intel 4...
Sep 29, 2025
P
They can do it exactly because of that: half of US stock market will be taking a hit to the face in case of anything dramatic
Sep 29, 2025
S
I doubt they can easily walk away from US cause TSMC relies on US customer which are at the mercy of US more or less an eternal cycle...
Sep 29, 2025
S
TSMC can walk away, and US will be stuck with Samsung's old plant. Which is a limited scale enterprise, built exactly for the purpose of...
Sep 29, 2025
S
From Wikichip N3B is ouch too many layers and info on how many layers Intel uses EVU from what i know on Intel 4 the EUV use is pretty...
Sep 29, 2025
S
N7 was all-DUV, N7P had some EUV layers but incompatible design rules so no IP porting. IIRC (we didn't use it) N6 was a shrunk N7 (with...
Sep 29, 2025
Daniel Nenni replied to the thread Intel splashes more cash on ASML’s magic machines.Yes I am sure. Would you dare to question Scotten Jones? ;) From TSMC: EUV process improves logic density; provides backward...
Haha.
If you think N3 was bad for EUV layers (and wafer prices!), you shouldn't even look at N2... ;-)
Like.
They can do it exactly because of that: half of US stock market will be taking a hit to the face in case of anything dramatic
Love.
Yes, N3B is 25 EUV layers and N3E is 19. TSMC calls it yield learning. Intel 4...