Array
(
[content] =>
[params] => Array
(
[0] => /forum/whats-new/latest-activity?before_id=103189
)
[addOns] => Array
(
[DL6/MLTP] => 13
[Hampel/TimeZoneDebug] => 1000070
[SV/ChangePostDate] => 2010200
[SemiWiki/Newsletter] => 1000010
[SemiWiki/WPMenu] => 1000010
[SemiWiki/XPressExtend] => 1000010
[ThemeHouse/XLink] => 1000970
[ThemeHouse/XPress] => 1010570
[XF] => 2030770
[XFI] => 1060170
)
[wordpress] => /var/www/html
)
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I read about this on various sites yesterday, and had to chuckle. How is it that Rivian, whose sales volume for 2025 is about 40,000...
Saturday at 7:19 AM
It’s interesting that Rivian is getting into the AI chip business and appears to be targeting industries more than just automotive...
Saturday at 6:53 AM
I think it is great to see another automotive company leveraging an advanced node (5nm). The chip appears to have 14 x Cortex A720AE...
Saturday at 6:31 AM
I think it is great to see another automotive company leveraging an advanced node (5nm). The chip appears to have 14 x Cortex A720AE...
Saturday at 5:31 AM
M
Not being a formal news, rumors from private network said ASML was forced to pending JSMC EUV delivery indefinitely for some...
Saturday at 5:04 AM
S
Node shrink will continue to matter than cause while density benefits have been lowered but Power and performance still continue to scale
Saturday at 3:47 AM
They all use the same fab process although HBM add TSVs - basically do a new design and run it through the fab. There is no downtime...
Saturday at 2:29 AM
F
Appreciate all the discussion and accurate numbers on minimum pitches and raw maximum cell densities, but without any discussion of...
Friday at 10:13 PM
F
I'd picture it this way...
Friday at 10:12 PM
L
118mtr is my guess.
By the way, a Chinese forum post an information, not sure if this is true.
He mention that N+3 gate pitch is 57nm...
Friday at 9:26 PM
J
you dont recover glory. The gain new glory.
Intel was a dominant execution engine in the past with no competitor who could succeed...
Friday at 8:38 PM
J
Are they using some new ultra high density library?
Friday at 8:38 PM
J
N+2 is 93 mtr.
It has 63nm gate pitch and 252nm cell height which revealed by Techinsight.
118 mtr mean ~27% density improve, very huge.
Friday at 8:31 PM
S
I suspect that quantum computing will blow the current state of the art semiconductor technology and optical computing out of the water...
Friday at 7:52 PM
S
They all use the same fab process although HBM add TSVs - basically do a new design and run it through the fab. There is no downtime...
Friday at 7:01 PM