Xiangdi 5nm GPU completes tape-out verification

[Fred Chen]

On September 3, Anfu Technology stated on its interactive platform that the new generation "Fuxi" architecture chip developed by Xiangdi has completed tape-out verification. The chip performs excellently in terms of graphics rendering capabilities and parallel computing performance.

It is reported that the chip uses a 5nm process, has a computing power of 160TFLOPS (FP32), integrates 12GB HBM2 video memory, has excellent graphics rendering and parallel computing performance, and after optimization, it has the technical foundation to run "Black Myth: Wukong". Currently, game adaptation testing is underway.

It is reported that the "Fuxi" architecture will launch two new products with leading domestic levels: Fuxi A0 fills the gap in domestic high-end rendering, and Fuxi B0 (GPU+NPU fusion) is mainly aimed at the AIPC market, supporting edge deployment of mainstream models such as LLAMA and Sora (it was disclosed in April that the chip was in the tape-out stage).

In 2025, Xiangdi completed a new round of strategic financing worth hundreds of millions of yuan, with Anfu Technology, an A-share listed company, participating in this round of financing.

Founded in 2020, Xiangdi is a high-performance general-purpose/dedicated processor chip design company. The company develops high-performance, low-power general-purpose CPUs/GPUs and related dedicated chips with complete independent intellectual property rights, suitable for desktops, workstations, edge computing, and other fields.

象帝先（5nm）GPU完成流片验证-全球半导体观察

9月3日，安孚科技9月3日在互动平台表示，象帝先研发的新一代“伏羲”架构芯片已完成流片验证

www.dramx.com

 

[Fred Chen]

This development, which happened a little over two months ago, may not signify much in the GPU world (compared to Huawei and NVIDIA obviously), but a 5nm GPU tapeout in China at this point is significant, since last November TSMC and Samsung have stopped shipping AI-related chips at 7nm and below to China. So it indicates a 5nm domestic process establishment, probably at SMIC.

Exclusive: US ordered TSMC to halt shipments to China of chips used in AI applications

The US order comes just weeks after TSMC notified that one of its chips had been found in a Huawei AI processor.

www.reuters.com

繼台積電後，傳三星也斷供中國 7 奈米以下晶片

台積電斷供中國 7 奈米以下晶片，近日傳韓國三星晶圓代工部門也向中國客戶發出停止供貨通知。 三星表示，無法評論與客戶相關的事宜。但中媒報導，算力晶片企業股東人士稱，三星與台積電近日寄信給他投資的企業，要求客戶配合審查投片資格。 台積電發函給中國 AI 晶片企業客戶，暫停 7 奈米以下先進製程代工。中...

technews.tw

 

[samwu1998]

SMIC’s “7nm” output is extremely small
It barely covers the needs of Huawei’s Mate-series SoCs (Kirin 9000S/9010/9020) and Ascend GPU. Low yield, extremely high cost, and nowhere near enough even for Huawei phones SoC and GPU.
CCP explicitly treats “advanced nodes” as national strategic resources. Huawei = “highest-priority national project with maximum geopolitical value.”
Their 7nm and hypothetical 5nm capacity = political asset.
Therefore:
If Huawei can’t get enough 7nm capacity, how could SMIC possibly give nonexistent 5nm to Xiangdixian — a company on the verge of bankruptcy?

 

[Fred Chen]

SMIC’s “7nm” output is extremely small
It barely covers the needs of Huawei’s Mate-series SoCs (Kirin 9000S/9010/9020) and Ascend GPU. Low yield, extremely high cost, and nowhere near enough even for Huawei phones SoC and GPU.
CCP explicitly treats “advanced nodes” as national strategic resources. Huawei = “highest-priority national project with maximum geopolitical value.”
Their 7nm and hypothetical 5nm capacity = political asset.
Therefore:
If Huawei can’t get enough 7nm capacity, how could SMIC possibly give nonexistent 5nm to Xiangdixian — a company on the verge of bankruptcy?

Xiangdixian is the key player here; it almost dissolved last year, but apparently got bailed out by Anfu (a battery developer?), probably with government arrangement.

At its website, Xiangdixian maintains it is doing domestic GPU production; it previously used 12nm, which likely came from TSMC (not sure SMIC has 12nm).

Anfu recently also maintained everything going ok so far: https://u.95579.com.cn/cjscweb/web/...=MzcwNzM1ZTY5ZDkzYjY5ODJiMTFmODk0MjdiYzc2ZTY=

 

[samwu1998]

Anfu sales and net profit in 2024 is less than $700M and $25M, respectively, in 2024, and fund a 5nm GPU SoC design which cost at least $500M?

 

[Barnsley]

Am waiting for the Expert inputs on SMIC

 

[Daniel Nenni]

According to a friend at Huawei they have an SMIC based 5nm processor in production. It is a Kirin X90? They also have a 5nm SoC in process. I will be at IEDM next month, maybe we will hear more about it then. Scotten Jones will be there as well. There are no SMIC papers but the hallway talk should have something.

 

[LLL0955]

According to a friend at Huawei they have an SMIC based 5nm processor in production. It is a Kirin X90? They also have a 5nm SoC in process. I will be at IEDM next month, maybe we will hear more about it then. Scotten Jones will be there as well. There are no SMIC papers but the hallway talk should have something.

X90 is N+2 process, not 5nm. Techinsight has decap X90 and found the gate pitch and cell height is the same as Kirin 9000S-Kirin 9020.

 

[Daniel Nenni]

X90 is N+2 process, not 5nm. Techinsight has decap X90 and found the gate pitch and cell height is the same as Kirin 9000S-Kirin 9020.

I was told N+3.

 

[Fred Chen]

X90 is N+2 process, not 5nm. Techinsight has decap X90 and found the gate pitch and cell height is the same as Kirin 9000S-Kirin 9020.

I remember the X90 teardown now. I hadn't known it had been promoted by the state as 5nm the month before. The teardown must have truly caused some embarrassment, TechInsights now blacklisted in China. But what's more significant is whether Huawei itself had considered X90 any generation beyond "N+2". If so, that would be truly disappointing, although similar node re-designations have been done before by Samsung and Intel.

I was told N+3.

I had heard the term "N+3" before, but apparently if this is X90, according to TechInsights, it's not visibly different from "N+2".

 

[Daniel Nenni]

I remember the X90 teardown now. I hadn't known it had been promoted by the state as 5nm the month before. The teardown must have truly caused some embarrassment, TechInsights now blacklisted in China. But what's more significant is whether Huawei itself had considered X90 any generation beyond "N+2". If so, that would be truly disappointing, although similar node re-designations have been done before by Samsung and Intel.

I had heard the term "N+3" before, but apparently if this is X90, according to TechInsights, it's not visibly different from "N+2".

Maybe it was the Kirin 9000, my mistake:

Cutting-edge 5 nm manufacturing and up to 15.3 billion transistors make this 5G SA solution available in the smallest footprint possible. The brand-new Arm Cortex-A77 CPU ensures superior performance while the groundbreaking 24-core Mali-G78 GPU enables uninterrupted gaming. Two big and one tiny core support AI video applications with better energy efficiency. The NPU is integrated with an embedded Kirin ISP 6.0 for camera functions – HDR video synthesis with real-time exposure to excel in lowlight and backlit conditions.

Kirin 9000 Chipset | HiSilicon Official Site

Kirin 9000 is the most mature 5G SA solution in the industry. It brings users a fast 5G existing network experience. It newly upgrades Cortex-A77 CPU. The main frequency of the large core exceeds 3.1Ghz. It adopts Huawei Da Vinci architecture 2.0 NPU. The dual large core shows outstanding AI...

www.hisilicon.com

 

[KevinK]

Am waiting for the Expert inputs on SMIC

From Perplexity on 7nm, with references:

SMIC’s 7nm production capacity in late 2025 is estimated between 30,000 and 45,000 wafers per month, and the company aims to roughly double this capacity in 2026, responding to robust demand from domestic clients, particularly Huawei and emerging AI chip suppliers.[1][2][3][4]

## Current Production Capacity

- As of Q4 2025, SMIC is reliably producing over 30,000 12-inch wafers per month at the 7nm node, with some estimates placing overall advanced node capacity (7nm and below) at up to 45,000 wafers per month.
- There are plans and investment initiatives to further expand this, targeting a capacity near 60,000 wafers per month by 2026.
- The ramp-up is supported by China’s broader push towards supply-chain localization, and several new factories connected to SMIC and Huawei are expected to come online through 2026.[2][3][5][4][1]

## Yield Status

- Yields for SMIC 7nm processes have improved over the past year, reaching a range between 60% and 70% for DUV-based processes in the second half of 2025.[6][3][7]
- This is a significant advance compared to earlier yields (below 40% in late 2023 and early 2024), and now approaches commercial thresholds that support mass-market production for devices such as Huawei’s Kirin processors.[7][8][6]
- SMIC’s 7nm yield remains lower than TSMC’s EUV-based 7nm (which exceeds 75%), limiting overall supply—still, it is sufficient for profitable production and supports the scaling of China’s domestic AI and mobile chip industries.[8][6][7]

## Industry Context

- The lack of EUV lithography technology (due to ongoing U.S. and Dutch export controls) means SMIC’s 7nm is achieved through multiple complex DUV layers, and production costs remain high from expensive and rapid depreciation.
- Several Chinese firms (e.g., Cambricon, Biren) are increasingly using SMIC’s capacity, driving high utilization rates and strategic shifts in domestic chip supply.[5][2][6]

In summary, SMIC’s 7nm line is now stable, high-volume, and commercially viable, with yields continuing to improve, though still trailing global competitors on efficiency and cost.[3][6][7]

Sources
[1] Huawei Ascend Production Ramp: Die Banks, TSMC Continued ... https://newsletter.semianalysis.com/p/huawei-ascend-production-ramp
[2] [News] SMIC 1H25 Net Profit Rises 35.6%, 7nm Capacity ... https://www.trendforce.com/news/202...-6-7nm-capacity-reportedly-to-double-in-2026/
[3] SMIC Q2 2025 Earnings and Commentary - SemiWiki https://semiwiki.com/forum/threads/smic-q2-2025-earnings-and-commentary.23371/
[4] steve hsu on X

https://twitter.com/x/status/1925890994345591255

[5] China's chip industry will surprise the world - The Economist https://www.economist.com/the-world-ahead/2025/11/12/chinas-chip-industry-will-surprise-the-world
[6] Can China Make 5nm Chips? - Semiecosystem https://marklapedus.substack.com/p/can-china-make-5nm-chips
[7] SMIC Projects 9B Revenue by 2025 Amid Chip Demand - LinkedIn https://www.linkedin.com/posts/adli...o-exceed-9b-activity-7395335942279987200-GJcw
[8] How is SMIC after US embargo? - Andy Lin https://www.granitefirm.com/blog/us/2025/03/08/smic-after-us-embargo/
[9] SMIC 7nm technology found in MinerVa Bitcoin Miner - TechInsights https://www.techinsights.com/blog/disruptive-technology-7nm-smic-minerva-bitcoin-miner
[10] SMIC H1 2025: Net Profit Surges 35.6%, 7nm Capacity Set to ... https://techovedas.com/smic-h1-2025-net-profit-surges-35-6-7nm-capacity-set-to-double-in-2026/
[11] SMIC's Q2 2025 Earnings: A Test of Resilience in a Pressured ... https://www.ainvest.com/news/smic-q...ience-pressured-semiconductor-landscape-2508/
[12] SMIC AI Chip Production Faces Major Setback Morgan Stanley Cuts ... https://www.technetbooks.com/2025/09/smic-ai-chip-production-faces-major.html
[13] [PDF] Strengthening Export Controls on Semiconductor Manufacturing ... https://www.congress.gov/119/meetin...es/HHRG-119-FA19-Wstate-McGuireC-20251120.pdf
[14] News of SMIC's bid to double 7-nm chip production sees stock surge ... https://www.thestandard.com.hk/mark...nm-chip-production-sees-stock-surge-over-10pc
[15] China's Semiconductor Investment Defies Economics—But Makes ... https://sinosoutheastinitiative.com...-economics-but-makes-perfect-strategic-sense/
[16] Semiconductor Manufacturing International Corporation (SMIC) https://www.scmp.com/topics/semiconductor-manufacturing-international-corporation-smic
[17] Made in China 2025: Evaluating China's Performance https://www.uscc.gov/research/made-china-2025-evaluating-chinas-performance
[18] Can SMIC Help China Win the AI Race? - Disruption Banking https://www.disruptionbanking.com/2025/08/28/can-smic-help-china-win-the-ai-race/
[19] SMIC says worries over memory shortage prompt customers to hold ... https://www.reuters.com/world/china...mpt-customers-hold-back-q1-orders-2025-11-14/
[20] China's legacy chip dominance poses 'severe' threat, warns author ... https://www.digitimes.com/news/a20251117VL209/china-chips-smic-industrial-production.html

 

[KevinK]

Am waiting for the Expert inputs on SMIC

SMIC’s 5nm process uses advanced DUV multi-patterning and exhibits larger critical dimensions (CDs) compared to TSMC’s EUV-enabled 5nm.

## SMIC 5nm Critical Dimensions

- Reported gate length for SMIC 5nm is approximately 25-30 nm, which is a bit larger than TSMC’s nominal 5nm gate length but similar to previous-generation FinFET R&D numbers.[1][2]
- Fin pitch (distance between fins in FinFET) for industry 5nm is typically 25-28 nm; SMIC’s DUV process is likely at the upper end, so fin pitch may be close to 28 nm.[3][1]
- Metal pitch (distance between metal lines) is estimated to be 28-32 nm, larger than TSMC’s 25-28 nm, because multi-patterned DUV processes cannot achieve ultra-dense scaling.[1][3]
- Fin height for optimized 5nm FinFETs is about 50–60 nm, and fin widths should be around 5–6 nm for best drive/current and subthreshold control; SMIC devices may keep fin width closer to 6 nm for manufacturability.[4][1]
- SMIC’s effective density and minimum features therefore resemble a “5.5nm” class node (sub-30 nm features), rather than true “EUV” 5nm numbers.[5][6]

## Summary Table: SMIC vs. TSMC/Samsung (Approximate)

| CD (nm) | SMIC 5nm (DUV) | TSMC 5nm (EUV) | Samsung 5nm (EUV) |
|-------------------|:--------------:|:--------------:|:-----------------:|
| Gate length | 25–30[1] | ~22–25[3] | ~24–25[7] |
| Fin pitch | ~28[1][3] | 25–26[3] | ~27[7] |
| Metal pitch | 28–32[1][3] | 25–28[3] | ~28[7] |
| Fin height | 50–60[4] | 55–60[4] | 55[4][7] |
| Fin width | ~5–6[4][1] | 5[4][3] | 5[4][7] |

SMIC’s 5nm CD is competitive for internal-use “5nm” chips but achieves less density than TSMC/Samsung due to DUV limits on minimum pitches and resolution.[6][5][3][1]

Sources
[1] 5nm Vs. 3nm - Semiconductor Engineering https://semiengineering.com/5nm-vs-3nm/
[2] 5 nm process - Wikipedia https://en.wikipedia.org/wiki/5_nm_process
[3] The TRUTH of TSMC 5nm - by SkyJuice - Angstronomics https://www.angstronomics.com/p/the-truth-of-tsmc-5nm
[4] [PDF] The Effect of Fin Structure in 5 nm FinFET Technology http://www.jommpublish.org/static/p...56A6F248835F13A5A9/10.33079.jomm.19020405.pdf
[5] Can China Make 5nm Chips? - Semiecosystem https://marklapedus.substack.com/p/can-china-make-5nm-chips
[6] TSMC Tops New Foundry Rankings, Samsung Loses Ground https://marklapedus.substack.com/p/tsmc-tops-new-foundry-rankings-samsung
[7] TSMC and Samsung 5nm Comparison - SemiWiki https://semiwiki.com/semiconductor-...foundry/8157-tsmc-and-samsung-5nm-comparison/
[8] [News] SMIC Reported to Complete 5nm Chips by 2025, but Costs ... https://www.trendforce.com/news/202...y-2025-but-costs-may-be-50-higher-than-tsmcs/
[9] How could SMIC achieve 5 nm? - TechInsights https://www.techinsights.com/blog/how-could-smic-achieve-5-nm
[10] China's Struggle to Manufacture Advanced Semiconductors https://brief.bismarckanalysis.com/p/chinas-struggle-to-manufacture-advanced
[11] Samsung squeezed: TSMC scales 3nm heights, SMIC cracks 5nm https://www.digitimes.com/news/a20250602PD219/3nm-samsung-samsung-foundry-smic-5nm.html
[12] TSMC Details 5 nm - WikiChip Fuse https://fuse.wikichip.org/news/3398/tsmc-details-5-nm/
[13] SMIC to make its 5nm chips a reality in 2025, but things are not ideal https://www.androidheadlines.com/2025/03/smic-5nm-chips-2025.html
[14] Yield rate comparison of SMIC, Rapidus, TSMC, Samsung, Intel's ... https://www.granitefirm.com/blog/us/2022/05/13/yield-rate-comparison/
[15] Huawei, the leader in Chinese semiconductor development… 'Life ... https://semiwiki.com/forum/threads/...for-smic-5nm-mass-production-next-year.22690/
[16] TSMC 5nm vs Samsung 5nm: Is the hype around TSMC really ... https://smart.dhgate.com/tsmc-5nm-vs-samsung-5nm-is-the-hype-around-tsmc-really-justified/
[17] Ask the Experts: Is China's Semiconductor Strategy Working? - CSET https://cset.georgetown.edu/article/ask-the-experts-is-chinas-semiconductor-strategy-working/
[18] Huawei, SMIC struggle to advance chips to 5-nm level, MateBook ... https://www.scmp.com/tech/tech-war/...dvance-chips-5-nm-level-matebook-shows-report
[19] 7 nm process - Wikipedia https://en.wikipedia.org/wiki/7_nm_process
[20] Inside China's chip Challenge: On the Road in China - Walter Scott https://www.walterscott.com/inside-chinas-chip-challenge-on-the-road-in-china/

 

[Fred Chen]

- Metal pitch (distance between metal lines) is estimated to be 28-32 nm, larger than TSMC’s 25-28 nm, because multi-patterned DUV processes cannot achieve ultra-dense scaling.[1][3]

In publications (CSTIC, CN patents) they often do use 28 nm pitch or 30 nm pitch as examples. But whether that actually pans out, we'll have to see. TSMC N5 is in fact 28 nm MMP (35 nm track M2P).

 

[Barnsley]

SMIC’s 5nm process uses advanced DUV multi-patterning and exhibits larger critical dimensions (CDs) compared to TSMC’s EUV-enabled 5nm.

## SMIC 5nm Critical Dimensions

- Reported gate length for SMIC 5nm is approximately 25-30 nm, which is a bit larger than TSMC’s nominal 5nm gate length but similar to previous-generation FinFET R&D numbers.[1][2]
- Fin pitch (distance between fins in FinFET) for industry 5nm is typically 25-28 nm; SMIC’s DUV process is likely at the upper end, so fin pitch may be close to 28 nm.[3][1]
- Metal pitch (distance between metal lines) is estimated to be 28-32 nm, larger than TSMC’s 25-28 nm, because multi-patterned DUV processes cannot achieve ultra-dense scaling.[1][3]
- Fin height for optimized 5nm FinFETs is about 50–60 nm, and fin widths should be around 5–6 nm for best drive/current and subthreshold control; SMIC devices may keep fin width closer to 6 nm for manufacturability.[4][1]
- SMIC’s effective density and minimum features therefore resemble a “5.5nm” class node (sub-30 nm features), rather than true “EUV” 5nm numbers.[5][6]

## Summary Table: SMIC vs. TSMC/Samsung (Approximate)

| CD (nm) | SMIC 5nm (DUV) | TSMC 5nm (EUV) | Samsung 5nm (EUV) |
|-------------------|:--------------:|:--------------:|:-----------------:|
| Gate length | 25–30[1] | ~22–25[3] | ~24–25[7] |
| Fin pitch | ~28[1][3] | 25–26[3] | ~27[7] |
| Metal pitch | 28–32[1][3] | 25–28[3] | ~28[7] |
| Fin height | 50–60[4] | 55–60[4] | 55[4][7] |
| Fin width | ~5–6[4][1] | 5[4][3] | 5[4][7] |

SMIC’s 5nm CD is competitive for internal-use “5nm” chips but achieves less density than TSMC/Samsung due to DUV limits on minimum pitches and resolution.[6][5][3][1]

Sources
[1] 5nm Vs. 3nm - Semiconductor Engineering https://semiengineering.com/5nm-vs-3nm/
[2] 5 nm process - Wikipedia https://en.wikipedia.org/wiki/5_nm_process
[3] The TRUTH of TSMC 5nm - by SkyJuice - Angstronomics https://www.angstronomics.com/p/the-truth-of-tsmc-5nm
[4] [PDF] The Effect of Fin Structure in 5 nm FinFET Technology http://www.jommpublish.org/static/p...56A6F248835F13A5A9/10.33079.jomm.19020405.pdf
[5] Can China Make 5nm Chips? - Semiecosystem https://marklapedus.substack.com/p/can-china-make-5nm-chips
[6] TSMC Tops New Foundry Rankings, Samsung Loses Ground https://marklapedus.substack.com/p/tsmc-tops-new-foundry-rankings-samsung
[7] TSMC and Samsung 5nm Comparison - SemiWiki https://semiwiki.com/semiconductor-...foundry/8157-tsmc-and-samsung-5nm-comparison/
[8] [News] SMIC Reported to Complete 5nm Chips by 2025, but Costs ... https://www.trendforce.com/news/202...y-2025-but-costs-may-be-50-higher-than-tsmcs/
[9] How could SMIC achieve 5 nm? - TechInsights https://www.techinsights.com/blog/how-could-smic-achieve-5-nm
[10] China's Struggle to Manufacture Advanced Semiconductors https://brief.bismarckanalysis.com/p/chinas-struggle-to-manufacture-advanced
[11] Samsung squeezed: TSMC scales 3nm heights, SMIC cracks 5nm https://www.digitimes.com/news/a20250602PD219/3nm-samsung-samsung-foundry-smic-5nm.html
[12] TSMC Details 5 nm - WikiChip Fuse https://fuse.wikichip.org/news/3398/tsmc-details-5-nm/
[13] SMIC to make its 5nm chips a reality in 2025, but things are not ideal https://www.androidheadlines.com/2025/03/smic-5nm-chips-2025.html
[14] Yield rate comparison of SMIC, Rapidus, TSMC, Samsung, Intel's ... https://www.granitefirm.com/blog/us/2022/05/13/yield-rate-comparison/
[15] Huawei, the leader in Chinese semiconductor development… 'Life ... https://semiwiki.com/forum/threads/huawei-the-leader-in-chinese-semiconductor-development…-‘life-or-death’-for-smic-5nm-mass-production-next-year.22690/
[16] TSMC 5nm vs Samsung 5nm: Is the hype around TSMC really ... https://smart.dhgate.com/tsmc-5nm-vs-samsung-5nm-is-the-hype-around-tsmc-really-justified/
[17] Ask the Experts: Is China's Semiconductor Strategy Working? - CSET https://cset.georgetown.edu/article/ask-the-experts-is-chinas-semiconductor-strategy-working/
[18] Huawei, SMIC struggle to advance chips to 5-nm level, MateBook ... https://www.scmp.com/tech/tech-war/...dvance-chips-5-nm-level-matebook-shows-report
[19] 7 nm process - Wikipedia https://en.wikipedia.org/wiki/7_nm_process
[20] Inside China's chip Challenge: On the Road in China - Walter Scott https://www.walterscott.com/inside-chinas-chip-challenge-on-the-road-in-china/

Only one poster in Semiwiki has the knowledge!

I will wait for them

 

[Fred Chen]

https://twitter.com/x/status/1993130386818527399

N+3 is still a guess though. There could still be a rude shock.