Arthur Hanson
Well-known member
Shrinkage has come to an end, will it be stacking, increase in energy efficiency, production processes or maybe even cost reductions? Are there any radical changes at all on the horizon?
What will be the next major advance in semis?
- Thread starter Arthur Hanson
- Start date
gc_epictetus
New member
Near term: advanced packaging, chiplets, 3D stacking.
Medium term: silicon photonics, CPO.
Long term: AI robots organize matter through telepathy displacing the need for fabs and manufacturing while we sit on the beach and sip drinks.
Medium term: silicon photonics, CPO.
Long term: AI robots organize matter through telepathy displacing the need for fabs and manufacturing while we sit on the beach and sip drinks.
Xebec
Well-known member
We may need a definition of radical 
-- New processes are already requiring many USD $B to come to market..
The DRAM roadmap seems to be focused on 3D stacking, Samsung estimating 2030 or later:
Logic - the IMEC roadmap now goes out to 2039 with newer transistor types coming. We're transitioning from FinFET to GAAFET now (also known as Nanosheet), the IMEC roadmap shows "CFET" around 2031 (7A process?), and "2DFET?" as the next type around 2037 or so (2A process tentatively). That indicates about 6 years / 3 "nodes" per transistor type, compared to ~ a really long time for Planar, and ~ 13 years for FinFET.
www.imec-int.com
I think NAND / Flash memory still has some headroom to go with cell changes (5-6 levels per cell) on top of more 3D stacking.
As far as the machinery goes -- High NA and "Hyper NA" are in development. Pat Gelsinger has indicated High NA may help lower costs per transistor, though a lot of others here have disagreed (with good arguments from what I understand).
-- New processes are already requiring many USD $B to come to market.. The DRAM roadmap seems to be focused on 3D stacking, Samsung estimating 2030 or later:
Logic - the IMEC roadmap now goes out to 2039 with newer transistor types coming. We're transitioning from FinFET to GAAFET now (also known as Nanosheet), the IMEC roadmap shows "CFET" around 2031 (7A process?), and "2DFET?" as the next type around 2037 or so (2A process tentatively). That indicates about 6 years / 3 "nodes" per transistor type, compared to ~ a really long time for Planar, and ~ 13 years for FinFET.
2D-material based devices in the logic scaling roadmap | imec
2D materials are promising to extend the logic technology roadmap, but developments are needed towards industrial adoption. Read about imec’s unique approach.
I think NAND / Flash memory still has some headroom to go with cell changes (5-6 levels per cell) on top of more 3D stacking.
As far as the machinery goes -- High NA and "Hyper NA" are in development. Pat Gelsinger has indicated High NA may help lower costs per transistor, though a lot of others here have disagreed (with good arguments from what I understand).