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Was reading through http://www.eetindia.co.in/ART_8800716410_1800007_NT_d1c0cba2.HTM
Compact SoC have been the key in smartphone advancement and article talks of SiP to be key for IoT (may be for flexibility of integrating only those blocks which are needed for particular application)
Anyone knows of SiP solutions already in market?
Can 3DIC be SiP solution for IoT needing small form factor
One way to build an electronic system is to place as much digital and analog content onto a single chip, called an SoC.
An alternative method to achieve similar results is to take these multiple digital and analog chips and assemble them into a single package, called an SiP. Popular examples of SiP today include:
From device perspective, Apple Watch is a nice example of SiP which has a 26mm x 28mm containing more than 30 components. From tools perspective Cadence Allegro platform provides good tools for SiP design. Also, Mentor has ADEP-SiP.
Going forward we are going to see more wafers packaged in 3D, the growth in density has to take vertical direction sooner than later.
So how does one test so many ICs of SiP. Is it just Wafer level test & system level test. Any tools to provide access to test individual IC on package so called package level test?
S1 processor image looks like a compact board of many dies; similar to PCB with many packaged ICs. So what's stopping from putting all you need into single SiP: only one package per electronic gadget?
Can 3D packaging go beyond single design house & single foundry case?
If apple S1 was to be 3D, ensuring compatibility (eg. pitch of pads) may need each of its components to be designed specifically for S1 and to allow designers to do so may need manufacturing from same foundry.
It has to go through all kinds of tests. For 3D-IC packaging wafer level test is a must, only KGD (Known Good Dies) can go in there. Now for system level test, the functionality, timing, power,.... the whole system has to be tested and that's a big problem today. A single chip is easier but a system requires all of different approaches - simulation, emulation, FPGA prototyping, and post silicon level testing. The big three EDA vendors and some others have tools for all of these kinds of verification.
The problem is that these approaches are disjoint and consume lot of resources, time and effort to create test infrastructure and then do the actual testing.
A good effort is going on to standardize the tests and testbenches so that they can be re-used across different verification engines as well as between IP, subsystem and the whole system. Accellera has established a work group, called Portable Stimulus Working Group (PSWG) that is working on standardizing this effort. Recently Cadence, Mentor and Breker donated there stuff to this group and are active members to come out with a workable standard across the semiconductor design industry. Read the article "Moving up Verification to Scenario Driven Methodology" for more details.
