TSMC N2 SRAM cell size hasn't scaled

[Fred Chen]

TSMC introduced a 38.1Mb/mm2 SRAM in 2nm-CMOS-nanosheet technology for high-density and energy-efficient compute applications. The design uses a 0.021um2 high-density bitcell, and through DTCO improves the overall SRAM density by 1.1× compared to the previous technology node.

https://research.tsmc.com/page/memory/4.html

This cell size is the same as N5 and N3E, as well as Intel 18A.

 

[siliconbruh999]

View attachment 3939

TSMC introduced a 38.1Mb/mm2 SRAM in 2nm-CMOS-nanosheet technology for high-density and energy-efficient compute applications. The design uses a 0.021um2 high-density bitcell, and through DTCO improves the overall SRAM density by 1.1× compared to the previous technology node.

https://research.tsmc.com/page/memory/4.html

This cell size is the same as N5 and N3E, as well as Intel 18A.

While the bticell didn't scaled the macro size did scale quite a lot

IEDM 2025 – TSMC 2nm Process Disclosure – How Does it Measure Up? - Semiwiki

Initial thoughts At IEDM held in December 2024, TSMC presented: “2nm Platform Technology featuring Energy-efficient Nanosheet Transistors and Interconnects co-optimized with 3DIC for AI, HPC and Mobile SoC Applications,” the authors are: Geoffrey Yeap, S.S. Lin, H.L. Shang, H.C. Lin, Y.C. Peng...

semiwiki.com

 

[essiah]

While the bticell didn't scaled the macro size did scale quite a lot
View attachment 3940

IEDM 2025 – TSMC 2nm Process Disclosure – How Does it Measure Up? - Semiwiki

Initial thoughts At IEDM held in December 2024, TSMC presented: “2nm Platform Technology featuring Energy-efficient Nanosheet Transistors and Interconnects co-optimized with 3DIC for AI, HPC and Mobile SoC Applications,” the authors are: Geoffrey Yeap, S.S. Lin, H.L. Shang, H.C. Lin, Y.C. Peng...

semiwiki.com

I have interacted with S.S. Lin and Y.C. Peng in the past

 

[Fred Chen]

While the bticell didn't scaled the macro size did scale quite a lot
View attachment 3940

IEDM 2025 – TSMC 2nm Process Disclosure – How Does it Measure Up? - Semiwiki

Initial thoughts At IEDM held in December 2024, TSMC presented: “2nm Platform Technology featuring Energy-efficient Nanosheet Transistors and Interconnects co-optimized with 3DIC for AI, HPC and Mobile SoC Applications,” the authors are: Geoffrey Yeap, S.S. Lin, H.L. Shang, H.C. Lin, Y.C. Peng...

semiwiki.com

It looks like the array area efficiency went from 68% to 80%.

 

[DanX]

try 3T SRAM

 

[Fred Chen]

try 3T SRAM

There have indeed been many <6-T SRAM proposals over the decades!

 

[Xebec]

There have indeed been many <6-T SRAM proposals over the decades!

What's been the main drawback of the smaller cells? is it performance, reliability, power? all of the above?

 

[Fred Chen]

What's been the main drawback of the smaller cells? is it performance, reliability, power? all of the above?

I just reviewed with ChatGPT. Four transistors for cross-coupled inverter is stabler against transistor variation and leakage, while two access transistors provide better margins.

 

[siliconbruh999]

@Fred Chen apparently there is no macro size improvement as well in N2 vs N3

https://twitter.com/x/status/1997601416173834248

 

[Xebec]

@Fred Chen apparently there is no macro size improvement as well in N2 vs N3

https://twitter.com/x/status/1997601416173834248

It seems that N3P = N2 for SRAM density then, but both of those have some density improvement vs N3E (Apple A18 Pro), and N3B (Various products). An enhanced N2 could provide further density improvements ..

 

[Fred Chen]

@Fred Chen apparently there is no macro size improvement as well in N2 vs N3

https://twitter.com/x/status/1997601416173834248

It looks like they improved N3 from 34 to 38 Mb/mm2, which is same as N2 currently. That's impressive using N3 design rules. Could the same be applied to N2, or is it already applied?

 

[Xebec]

It looks like they improved N3 from 34 to 38 Mb/mm2, which is same as N2 currently. That's impressive using N3 design rules. Could the same be applied to N2, or is it already applied?

My gut (uneducated, not a SME) is they'll scale a little further later, on an improved N2 process. TSMC is very conservative in it's approaches for new nodes, and there were some discussions on this forum (from actual experts ), that GAAFET should allow some SRAM density improvements ovef FinFET.