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Question for all of those hard design/eda folks on semiwiki
Given the finlex libs vaguely look like the above image, I was wondering how common is it in modern chip designs for clock sensitive blocks for be on separate rows (ie above or below) non clock sensitive blocks? Or is it more common for you to see something where std cell/block with low speed requirements are on the left or right of a std cell/block with high speed requirements?
Given the finlex libs vaguely look like the above image, I was wondering how common is it in modern chip designs for clock sensitive blocks for be on separate rows (ie above or below) non clock sensitive blocks? Or is it more common for you to see something where std cell/block with low speed requirements are on the left or right of a std cell/block with high speed requirements?
It's not just speed-sensitive blocks but also individual gates, when doing timing closure without FinFlex the tools will choose different transistor types to trade off speed/dynamic power vs. leakage (e.g. ULVT, LVT, SVT -- which can be mixed), FinFlex just adds another set of gate options to this. Clocks may use the higher-speed gates but so will critical paths.
Different FinFlex types are also used between different (relatively large) blocks depending on similar lower/speed tradeoffs, for example a high-performance core might use 3-2 fin, a low power core might use 2-1 fin.
It's not just speed-sensitive blocks but also individual gates, when doing timing closure without FinFlex the tools will choose different transistor types to trade off speed/dynamic power vs. leakage (e.g. ULVT, LVT, SVT -- which can be mixed), FinFlex just adds another set of gate options to this. Clocks may use the higher-speed gates but so will critical paths.
Different FinFlex types are also used between different (relatively large) blocks depending on similar lower/speed tradeoffs, for example a high-performance core might use 3-2 fin, a low power core might use 2-1 fin.
So if I am understanding it right designers will draw up their design and the EDA software will pick the best VTs for the design (presumably based on preferences the designer feeds to the software). In the case of finFLEX the eda software will look for rows across section of the die that can have the fin count scaled to maximize PPA in whatever way the designer told the software to prioritize?
So if I am understanding it right designers will draw up their design and the EDA software will pick the best VTs for the design (presumably based on preferences the designer feeds to the software). In the case of finFLEX the eda software will look for rows across section of the die that can have the fin count scaled to maximize PPA in whatever way the designer told the software to prioritize?
I'm not 100% sure how FinFlex mixing works, but I believe that you define the FinFlex configuration (1-1,1-2, 2-2, 2-3) for an HLB (High Level Block) depending on speed/power/density requirements -- mixed sizes are always alternating large/small rows -- and the tools then optimise (Vth and big/small row choice) within the HLB, which will typically have many rows of standard cells. There are also some double-height library cells which span 2 rows (e.g. 1-2 or 2-2 or 2-3).
It basically gives the tools a wider set of speed/power/density cells to choose from to optimise PPA, both within and across HLBs.
