K
Kamal Karimanal
Guest
See Similar articles at: http://www.cielution.com
As complex as the assembly of the package is, this article only requires some basic understanding of the fundamentals of thermally driven strains and stresses. In fact, we will include a short description here to lower the pre-requisite bar. There are many things that cause stresses during the packaging of the IC. If you leave out the emotional causes arising from stiff deadlines and demanding customers, the focus of the above mentioned stresses shift to inanimate subjects and the temperature difference between them.
Materials expand when they are heated, and shrink when cooled. They go about with these barely noticeable changes unless another material is stuck to it. The other material also wants to expand, but at a different magnitude depending on a property called Coefficient of Thermal Expansion (CTE). This proximity of dissimilar materials can lead to failure in IC packages when not managed carefully. (Starting to sound like the story of the cracked bottle of bear you left in the freezer and forgot? That's a completely different effect which we will save for another article.). The material with lower CTE wants to expand less and the material with higher CTE wants to expand more. The only way they can coexist is through warpage and stress build up in the materials. Figure shows the warpage effect under one scenario.
There is a reason why we used a cool down example in to illustrate the effect of CTE mismatch. The reason stems from the fact that all assembly attachment processes happen at high temperature and the package needs to come down to room temperature sooner or later. So, the coolest temperature experienced by the package causes the highest stresses in at the interfaces.
Armed with the above information we are ready to look at the steps during the assembly of an IC package and the stresses that are built. Figure shows the steps, and the corresponding qualitative warpage along with risk factors.
The risk factors can be mitigated by methodical tuning and matching of materials not only based on their CTE, but also their Modulus, physical dimensions such as thickness, footprint size as well as process condition options. Once this is achieved, the design and process conditions become the trade secret of the packaging company.
Now, imagine the above process steps on chips that are many folds thinner? What if these attach steps are repeated many times between thinned chips along with the steps described in the figure? That is the challenge of die stacking for 3D TSV technology. Based on the past record, it is only imperative that the packaging engineers will once again wave their magic wand and enable this next generation of microelectronics technology.
Simulation using Finite Element Analysis (FEA) has long been used by packaging engineers to study process step implications on reliability and yield. In addition to enabling package design and assembly process, FEA is also a tool used by packaging experts at fabless semiconductor companies to make calls on packaging technology roadmap and to perform form factor feasibility studies. Cielution's core competency includes the application of FEA to microelectronics packaging and reliability. This article only touched upon the tip of the packaging iceberg. Please contact us if we can help you with your next packaging challenge.
Thermo Mechanical Fundamentals of IC Package Design and Assembly
Assembling an IC in a package is an arcane field where systematic engineering leads to end products that are almost taken for granted. But everyone in the electronics supply chain knows that the importance of assembly. The assembly houses have been meeting every challenge thrown at it by narrowing form factors of the electronics products and shrinking technology nodes from the semi-conductor foundries. The above mentioned systematic engineering leverages many disciplines of science and technology. But in this article we shall look at how thermally and mechanically driven stresses and strains are leveraged and managed during the assembly of an IC.
As complex as the assembly of the package is, this article only requires some basic understanding of the fundamentals of thermally driven strains and stresses. In fact, we will include a short description here to lower the pre-requisite bar. There are many things that cause stresses during the packaging of the IC. If you leave out the emotional causes arising from stiff deadlines and demanding customers, the focus of the above mentioned stresses shift to inanimate subjects and the temperature difference between them.
Materials expand when they are heated, and shrink when cooled. They go about with these barely noticeable changes unless another material is stuck to it. The other material also wants to expand, but at a different magnitude depending on a property called Coefficient of Thermal Expansion (CTE). This proximity of dissimilar materials can lead to failure in IC packages when not managed carefully. (Starting to sound like the story of the cracked bottle of bear you left in the freezer and forgot? That's a completely different effect which we will save for another article.). The material with lower CTE wants to expand less and the material with higher CTE wants to expand more. The only way they can coexist is through warpage and stress build up in the materials. Figure shows the warpage effect under one scenario.
There is a reason why we used a cool down example in to illustrate the effect of CTE mismatch. The reason stems from the fact that all assembly attachment processes happen at high temperature and the package needs to come down to room temperature sooner or later. So, the coolest temperature experienced by the package causes the highest stresses in at the interfaces.
Armed with the above information we are ready to look at the steps during the assembly of an IC package and the stresses that are built. Figure shows the steps, and the corresponding qualitative warpage along with risk factors.
The risk factors can be mitigated by methodical tuning and matching of materials not only based on their CTE, but also their Modulus, physical dimensions such as thickness, footprint size as well as process condition options. Once this is achieved, the design and process conditions become the trade secret of the packaging company.
Now, imagine the above process steps on chips that are many folds thinner? What if these attach steps are repeated many times between thinned chips along with the steps described in the figure? That is the challenge of die stacking for 3D TSV technology. Based on the past record, it is only imperative that the packaging engineers will once again wave their magic wand and enable this next generation of microelectronics technology.
Simulation using Finite Element Analysis (FEA) has long been used by packaging engineers to study process step implications on reliability and yield. In addition to enabling package design and assembly process, FEA is also a tool used by packaging experts at fabless semiconductor companies to make calls on packaging technology roadmap and to perform form factor feasibility studies. Cielution's core competency includes the application of FEA to microelectronics packaging and reliability. This article only touched upon the tip of the packaging iceberg. Please contact us if we can help you with your next packaging challenge.