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Technical Highlights from the 2025 Symposium On VLSI Technology and Circuits (Intel 18A)

Daniel Nenni

Admin
Staff member
The 2025 Symposium on VLSI Technology and Circuits is a premiere international conference that records the pace, progress, and evolution of micro/nano integrated electronics, scheduled for June 8-12, 2025. The Symposium will be held in-person at the Rihga Royal Hotel, Kyoto Japan to foster networking opportunities.

The Symposium’s overall theme, " Cultivating the VLSI Garden: From Seeds of Innovation to Thriving Growth " integrates advanced technology developments, innovative circuit designs, and the applications that they enable as part of our global society’s transition to a new era of smart connected devices, infrastructure and systems that change the way humans interact with each other. The following are some of the highlight papers that address this theme:

Technology Highlights Advanced CMOS Technology “Intel 18A Platform Technology Featuring RibbonFET (GAA) and Power Via for Advanced High-Performance Computing” – Intel (Paper T1-1) An advanced Intel 18A technology featuring RibbonFET and Power Via provides over 30% density scaling and a full node of performance improvement compared to Intel 3. Intel 18A offers high-performance (HP) and high-density (HD) libraries with full-featured technology design capabilities and enhanced design ease of use. Figures:(Left)Intel 18A vs. Intel 3 PPA (Power, Performance, Area) comparison.

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PDF: https://www.vlsisymposium.org/wp-content/uploads/EN09_Technical-Tip-Sheet-VLSI-2025_EN_fin-1.pdf
 
It looks like Intel's HP and HD cells are differentiated by track pitch (36 nm vs. 32 nm), with fixed track number (5), whereas TSMC has fixed track pitch (26 nm) and differentiates by track number (6 vs. 5). Two pitches is more complicated lithographically (different pitches focus differently).
 
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