I list some papers I read from SPIE 2016, and their implications:
977610 EUV Patterning Successes and Frontiers (IBM/Globalfoundries/Samsung/TEL): Can't believe I missed this one! Cost of EUV single pass is about the same as three passes of 193i. So 2-mask SAQP (which is already published such as here: http://nanocad.ee.ucla.edu/pub/Main/SnippetTutorial/SAQP_YB.pdf) is more cost-effective in terms of litho tool throughput, but not 4- or 5-mask. Additionally, secondary electron blur is now affecting the EUV resolution limit necessary for N7 as SAQP replacement. The choice of underlying layer is constrained by this as well as resist pattern collapse.
97761Q Extension of practical k1 limit in EUV lithography (SK Hynix): basically 2x nm contact half-pitch would have trouble with EUV due to the stochastic nature of resist exposure.
97761R Application of EUV resolution enhancement techniques (RET) to optimize and extend single exposure bi-directional patterning for 7nm and beyond logic designs (GlobalFoundries and ASML Brion): 7nm (32 nm pitch) burdened by stochastic effects. 10 nm SRAF features added to masks (more write time, cost) to improve the imaging performance. SMO leads to quasar-like dipole illumination with lower pupil fill ratio, as would be expected from including intermediate pitches mainly in one direction. Even so, SMO inherently always favors one dense pitch over others, so effectively N7 will have design restrictions.
97761U EUV implementation of assist features in contact patterns (Mentor Graphics and IBM): 7nm node contacts need SRAFs (sub-resolution assist features) to preserve depth of focus >100 nm across pitch.
977616 EUV and optical lithographic pattern shift at the 5nm node (GlobalFoundries): At 5 nm, critical layers' (24 nm and 32 nm pitches) overlay window compromised by pattern shift from EUV, especially with high NA (anamorphic tools).
97761N Current development status of HSFET (High-NA Small Field Exposure Tool) in EIDEC (EIDEC/Toshiba/Zygo): This is a tool that aims to replicate the >0.5 NA tool before the availability of the anamorphic tool from ASML. Essentially, the high NA forces a central obscuration in the pupil which limits diffraction of larger pitches, forcing some more layout design restrictions.
97761W EUV patterned templates with grapho-epitaxy DSA at the N5/N7 logic nodes (IMEC and ASML Brion): At both N5 and N7, EUV stands to benefit from DSA first by increasing the required exposure CD and also by delivering some via multiplication (pitch multiplication). Otherwise EUV exposure dose would have to be increased to offset the shot noise effects.
97760A EUV lithography performance for manufacturing: status and outlook (ASML): So far ASML has not shipped any "final version" EUV tools fit for manufacturing. The NXE 3400 is expected to replace the NXE 3350 in 2017 and is not anamorphic (same NA), so EUV dipole multipatterning will be required. here: https://staticwww.asml.com/doclib/press/presentations/asml_20160226_SPIE_2016_EUV_overview.pdf
978102 Toward The 5nm Technology: Layout Optimization and Performance Benchmark for Logic/SRAMs Using Lateral and Vertical GAA FETs (IMEC, Vrije Universiteit): EUV double patterning required for N5 for multiple layers.
All in all, EUV is as far away as ever, and multiple patterning is inevitable.
977610 EUV Patterning Successes and Frontiers (IBM/Globalfoundries/Samsung/TEL): Can't believe I missed this one! Cost of EUV single pass is about the same as three passes of 193i. So 2-mask SAQP (which is already published such as here: http://nanocad.ee.ucla.edu/pub/Main/SnippetTutorial/SAQP_YB.pdf) is more cost-effective in terms of litho tool throughput, but not 4- or 5-mask. Additionally, secondary electron blur is now affecting the EUV resolution limit necessary for N7 as SAQP replacement. The choice of underlying layer is constrained by this as well as resist pattern collapse.
97761Q Extension of practical k1 limit in EUV lithography (SK Hynix): basically 2x nm contact half-pitch would have trouble with EUV due to the stochastic nature of resist exposure.
97761R Application of EUV resolution enhancement techniques (RET) to optimize and extend single exposure bi-directional patterning for 7nm and beyond logic designs (GlobalFoundries and ASML Brion): 7nm (32 nm pitch) burdened by stochastic effects. 10 nm SRAF features added to masks (more write time, cost) to improve the imaging performance. SMO leads to quasar-like dipole illumination with lower pupil fill ratio, as would be expected from including intermediate pitches mainly in one direction. Even so, SMO inherently always favors one dense pitch over others, so effectively N7 will have design restrictions.
97761U EUV implementation of assist features in contact patterns (Mentor Graphics and IBM): 7nm node contacts need SRAFs (sub-resolution assist features) to preserve depth of focus >100 nm across pitch.
977616 EUV and optical lithographic pattern shift at the 5nm node (GlobalFoundries): At 5 nm, critical layers' (24 nm and 32 nm pitches) overlay window compromised by pattern shift from EUV, especially with high NA (anamorphic tools).
97761N Current development status of HSFET (High-NA Small Field Exposure Tool) in EIDEC (EIDEC/Toshiba/Zygo): This is a tool that aims to replicate the >0.5 NA tool before the availability of the anamorphic tool from ASML. Essentially, the high NA forces a central obscuration in the pupil which limits diffraction of larger pitches, forcing some more layout design restrictions.
97761W EUV patterned templates with grapho-epitaxy DSA at the N5/N7 logic nodes (IMEC and ASML Brion): At both N5 and N7, EUV stands to benefit from DSA first by increasing the required exposure CD and also by delivering some via multiplication (pitch multiplication). Otherwise EUV exposure dose would have to be increased to offset the shot noise effects.
97760A EUV lithography performance for manufacturing: status and outlook (ASML): So far ASML has not shipped any "final version" EUV tools fit for manufacturing. The NXE 3400 is expected to replace the NXE 3350 in 2017 and is not anamorphic (same NA), so EUV dipole multipatterning will be required. here: https://staticwww.asml.com/doclib/press/presentations/asml_20160226_SPIE_2016_EUV_overview.pdf
978102 Toward The 5nm Technology: Layout Optimization and Performance Benchmark for Logic/SRAMs Using Lateral and Vertical GAA FETs (IMEC, Vrije Universiteit): EUV double patterning required for N5 for multiple layers.
All in all, EUV is as far away as ever, and multiple patterning is inevitable.
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