South Korea Says U.S. Chips Act Subsidies Have Too Many Requirements

[cliff]

Mr. Blue, did Intel outsource any designs to TSMC's DUV (above 7nm) processes, and why did they do that?

 

[Paul2]

Mr. Blue, did Intel outsource any designs to TSMC's DUV (above 7nm) processes, and why did they do that?

I recall their network chips, their wifi, their buck regulators, SSD controllers, RAID controller, compression accelerator chips, thunderbolt, optical transceivers for SFP modules, crypto accelerator chips, and few things they inherited from purchasing Altera

 

[blueone]

Mr. Blue, did Intel outsource any designs to TSMC's DUV (above 7nm) processes, and why did they do that?

In the past the primary reason for outsourcing chip designs to be fab'd at TSMC was low volume. Intel's manufacturing processing were optimized (and probably still are) around client high volumes, like 200-300 million+ units per year. Server CPUs, though they have volumes in 10s of millions of chips/year, were also fab'd by Intel because they used similar technology to the client CPUs. The same was true for client and server CPU chipsets. Other chips which had lower volumes, like networking chips, FPGAs, etc, were usually fab'd with TSMC, though I understand Altera's FPGAs used to be fab'd internally when Intel had a significant process lead.

Now everything is different, with Intel losing the process lead and tiled dies. Unless you have different information, most of what I see outsourced by Intel are the usual low volume chips, and chiplets where TSMC has a process lead. I also suspect that Intel wants to get the whole company on the foundry model to control internal development costs. Tiled dies are a big part of that, IMO. I remember being an advocate of tiled dies over 10 years ago. Huge multifunction dies often result in a bunch of all-layer steppings to get to GA, which is what the CPU teams seemed to experience. Assuming the design teams can produce leadership architectures (that remains to be seen), and assuming Intel gets back at least process parity, the tiled die strategy plays out, and the entire company develops using a foundry model, IMO Intel could regain some of the leadership it once enjoyed.

 

[Paul2]

I wouldn't say that Intel is that low volume either. By wafer volume they will stand ahead of pretty much all 3rd tier fabs.

 

[cliff]

Let's face it, TSMC is far better for the US design houses, and some of Intel's design groups!. Fund the foundries and equipment who help US design houses. Intel should get nothing.

 

[blueone]

I wouldn't say that Intel is that low volume either. By wafer volume they will stand ahead of pretty much all 3rd tier fabs.

What Intel defines as high volume is different than other companies, except perhaps memory companies. Intel CPU unit volume is probably about the same or in a good year greater than Apple's iPhone + iPad volume combined.

 

[benb]

My thoughts/speculations:
-Korea feedback is important, they have been in the US the longest. So Raimondo should listen.
-This is just the beginning of the strings, they still haven’t elaborated on what “2 manufacturing hubs” means.
-One thing it could mean is 2 science parks, like Hsinchu or Taichung. The location would be two US cities of course. Blue state? One red one blue? Opposite sides of the Mississippi?
-Once you are talking science park, the profit sharing, childcare and no stock buyback (making this more of a startup flavored place) makes more sense.
-It would be a good idea if TSMC, Samsung and Intel formed subsidiaries to operate in this park. If the subsidiary was headed by a POC, all the better. That is how you join the government gravy train, lots of prominent POCs, childcare for all, profit sharing, and yes, this is socialism, with democratic characteristics.