SK hynix Presents Future DRAM Technology Roadmap at IEEE VLSI 2025

[Fred Chen]

Seoul, June 10, 2025​

SK hynix Inc. (or “the company”, www.skhynix.com) announced today that it presented a new DRAM technology roadmap for the next 30 years and the direction for a sustainable innovation at the IEEE VLSI symposium 20251 held in Kyoto, Japan.

Cha Seon Yong, Chief Technology Officer (CTO) of SK hynix, delivered on June 10th a plenary session on “Driving Innovation in DRAM Technology: Towards a Sustainable Future”.

In his speech, CTO Cha explained that it is increasingly difficult to improve performance and capacity with scaling through current technology platform. “In order to overcome such limitations, SK hynix will apply the 4F² VG (Vertical Gate) platform and 3D DRAM technology to technologies of 10-nanometer level or below with innovation in structure, material and components,” he said.

The 4F² VG platform is a next-generation memory technology that minimizes the cell area of DRAM and enables high-integration, high-speed and low-power through a vertical gate structure.

Currently, 6F² cells are common, but by applying 4F² cell and wafer bonding technology that puts the circuit part below the cell area, cell efficiency and electrical characteristics can be improved.

CTO Cha also introduced 3D DRAM as the main pillar for the future DRAM along with VG. CTO Cha said that although some in the industry warn of cost increase according to the number of layers stacked, it can be solved by constant technological innovation.

Along with structural breakthrough, the company will also strive to find a new growth engine by sophisticating technologies of critical materials and components of DRAM to lay foundation for the next 30 years.

“Until around 2010, DRAM technology was expected to face limitations at 20 nanometers, but with constant innovation, we have made it this far,” said CTO Cha. “SK hynix will continue to guide the future of long-term technological innovation to be a milestone for young engineers in the field of DRAM and maintain cooperation within the industry to bring future of DRAM into reality.”

On the last day of the event, Joodong Park, vice president who leads the Next Gen DRAM TF, will present his findings from a recent research on how VG and wafer bonding technology affect the electrical characteristics of DRAM.

SK hynix Presents Roadmap for Future DRAM at IEEE VLSI 2025

SK hynix is participating in the 2025 Symposium on VLSI Technology and Circuits in Kyoto, Japan June 8-12, where it will present its long-term plans for DRAM.

news.skhynix.com

 

[jensy]

Is 4F² VG or 3D DRAM possible within 5 years？

 

[Fred Chen]

Is 4F² VG or 3D DRAM possible within 5 years？

6F² scaling is now coming up against the issue of shrinking gap between bit line and storage node contact. On the other hand, 4F² has the issue of word lines too close for cell sizes <0.0009 um². So 3D DRAM probably should be expedited.

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[benb]

Samsung V-NAND was introduced in 2013. That brought a lot of advantages, notably no longer needing to shrink dimensions, but rather build up more layers. That in turn enabled storing more than 1 bit per cell. Soon we may see 5 bits per cell.

Whereas DRAM has been stuck. Why has 3D DRAM taken this long? 12 years since V-NAND. Could we see more than 1 bit stored per cell?

 

[Fred Chen]

Samsung V-NAND was introduced in 2013. That brought a lot of advantages, notably no longer needing to shrink dimensions, but rather build up more layers. That in turn enabled storing more than 1 bit per cell. Soon we may see 5 bits per cell.

Whereas DRAM has been stuck. Why has 3D DRAM taken this long? 12 years since V-NAND. Could we see more than 1 bit stored per cell?

The 3D NAND could use vertical polysilicon channels, while the 3D DRAM needs horizontal channels, preferably not polysilicon. Reliability is of utmost importance, so SLC is a must.