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hi all
i have gds file from digital design in encounter.i imported this in cadence and i want check DRC&LVS with calibre.
i can check DRC but because i haven't a schematic from layout i can't check LVS.
please help me(((((((((((((((((((((((
best regards
Ask the other engineers in your group for the rest of the design files so that you can create a schematic netlist. You typically create a schematic netlist from a Standard Cell library and gate-level output from a logic synthesis tool.
dear daniel
tnx a lot for replay.i get netlist in encounter and add it in cadence. i can import the gds file in cadence and check DRC,but in LVS checking the calibre can't know the design VDD and VSS pad and all metal layer.
maybe the tool need .cdl file that creat from schematic?!!!!!!!!!!!!
Daniel
tnx a lot for help.did you any know about other way for Digital post layout simulation?
i know can simulate with vcs or hsim or hspice , but i do not know how they do it?!!!!!!!!!!!!!!!!!!!
best regards
For digital post-layout simulation you can extract the parasitic interconnect, create an SDF file, then re-simulate with your RTL or gate-level simulator to verify that your functional stimulus still works with accurate timing.
Another common technique is to run a Static Timing Analysis tool with the SDF file to find critical paths and determine the maximum clock speeds.
Daniel
tnx a lot for help.did you any know about other way for Digital post layout simulation?
i know can simulate with vcs or hsim or hspice , but i do not know how they do it?!!!!!!!!!!!!!!!!!!!
best regards
It all depends what is your exact requirement. For structural checks of netlist you can use Logic equivalence checks, for timing STA is a good option. For everything else GLS can be used though it will be time consuming. The process is the same as RTL simulation where you have a TB with Netlist as DUT now. The SDF can be annotated using $sdf_annotate to respective modules of the netlist and run tests on the same. If you can share a high level of the digital side that would help.
gauravjalan,
what is the GLS?
i get verilog netlist in encounter and simulated with standard cell library in modelsim or active HDL but how can make use of SDF or RTL?
what tool are needed for this work?
another question , how can get area report in SOC?
GLS is Gate level simulation aka Netlist simulation. You can do it with zero/unit delay with simulator options OR pursue a timing simulation of netlist with SDF. RTL is not coming into picture except that a subset of the verification vectors can be simulated at netlist level with SDF. SDF is standard delay format and is available pre-layout using wire load models or post layout that is accurate SDF. Any simulation tool like Questasim/Modelsim, NCSIM or VCS can do the needful. I didn't get you question on area report but if you are asking for the die size, back end tools can help.
For more on GLS you can search on google/ search on semiwiki for GLS/ siddhakarana
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