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NVIDIA’s CEO Claims That They Have No Option Other Than TSMC For Chips, Rules Out Partnership With Intel & Samsung Foundry In The US

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NVIDIA's CEO Jensen Huang has reaffirmed the company's commitment to TSMC, claiming that Team Green has no other "suitable" alternatives to the Taiwan giant.

NVIDIA's CEO Says TSMC Is The Leader In CoWoS, The Advanced Packaging Technology Which Defied Moore's Law

NVIDIA has been a key partner for TSMC for several years now, but the company has specifically deepened its cooperation after the initial AI hype. The partnership has evolved to a point where Team Green's CEO now says there's no alternative to the Taiwan giant, especially in the CoWoS department. Speaking at the GTC Taipei Global Press Conference, NVIDIA's Jensen Huang revealed that the company's semiconductor supply chain will rely entirely on TSMC in the near future, indicating that alternatives from Samsung Foundry or Intel haven't worked out for them.

When Jensen was asked whether NVIDIA would consider a partner other than TSMC for semiconductors, especially in the US, here's what he had to say:

This is a very advanced packaging technology. I'm sorry we don't have any other choice at the moment," and pointed out that TSMC is still the only partner.

One of the key reasons why NVIDIA has managed to bring such high performance to the table is that the company has managed to defy Moore's Law by integrating technologies such as CoWoS, since the packaging technology allowed Team Green to stack multiple chips together, combining performance and bringing it to levels which couldn't have been done by node shrinking. Jensen claims that there's no alternative to CoWoS, and based on industry reports, we know that TSMC holds the reins in the advanced packaging segment.

Team Green was reportedly collaborating with Samsung and Intel for advanced packaging, but it seems no deal has been formulated yet. Similarly, on the chip frontier, NVIDIA is a primary partner of TSMC and has even crossed Apple when it comes to the valuation of orders placed with the Taiwan giant. Apart from this, NVIDIA has played a massive roel in TSMC's US expansion as well, being the major customer for the company's regional operations.

So it is safe to say that an NVIDIA-TSMC partnership will go a long way, as stated by Jensen at the Computex keynote, and with the Taiwan giant expanding into the US, Team Green will be free from geopolitical uncertainties.

 
The following thread is similarly addressing the government's typical bone-headed rule by the least competent, often resulting in unforced errors.

Chip controls and tariffs are backfireing, and will very likely have unintended consequences.

 
Even if intel has much more superior packaging technologies and much more competitive pricing , I would guess that both Nvidia and Amd would continue to choose Tsmc or at the most Samsung.
I don’t think that they are afraid that Intel will copy their chip design for Intel products , but just giving business to Intel foundry would provide valuable cash flow that can help Intel products to compete with them. This fear or unwillingness to indirectly benefit your competitor, I believe is one big hurdle for Intel foundry.
Such fear is especially prominent in some culture, traditions or customs. In some cases, it’s extreme where that’s the number one objective, nothing else matters.
While I think it’s not the right time to separate Intel foundry now, I believe this very behavior traits is a strong reason to separate Intel foundry eventually.
 
I'd have thought that yield is another big reason. Given that Nvidia use reticle-size dies the die yield/cost is heavily dependent on D, and with their massive volumes for many products TSMC are better than anyone else at this -- certainly far better than Samsung for who this has always been a weak spot, and almost certainly also Intel who used to use high ASP to hide yield lower than TSMC.

If you have a 26mm x 33mm die and it has 20% yield at TSMC (only an example, not an actual number!) then it could easily have 10% or lower yield at Samsung/Intel, which would be a disaster for Nvidia when they're already capacity-constrained and can't keep up with demand...
 
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I'd have thought that yield is another big reason. Given that Nvidia use reticle-size dies the die yield/cost is heavily dependent on D, and with their massive volumes for many products TSMC are better than anyone else at this -- certainly far better than Samsung for who this has always been a weak spot, and almost certainly also Intel who used to use high ASP to hide yield lower than TSMC.
That is true
If you have a 26mm x 33mm die and it has 20% yield at TSMC (only an example, not an actual number!) then it could easily have 10% or lower yield at Samsung/Intel, which would be a disaster for Nvidia when they're already capacity-constrained and can't keep up with demand...
One flaw Intel also has done large dies many times and their yields has been good except for 10nm ofc.
GNR die is ~598mm2.
Also Nvidia uses the process after good bit of maturity
 
I suspect the way you get those reticle sized die to yield is picking a particular golden path through TSMC massive group of fabs. This is a competitive advantage that cannot be duplicated elsewhere, because it depends on having a massive fab network which only TSMC has.
 
That is true

One flaw Intel also has done large dies many times and their yields has been good except for 10nm ofc.
GNR die is ~598mm2.
Also Nvidia uses the process after good bit of maturity
Yes Intel has done large dies, but that still doesn't mean they had yield comparable with TSMC on them -- when you're an IDM selling a high-end HPC CPU for $10000 it doesn't matter so much if the yield is lower because this is hidden from your customers, there's no direct competition, and your overall product margin and profit is still massive.

Everything I've ever heard from people who actually know about real Intel yield and wafer costs says that compared to TSMC their wafer costs have always -- over many process nodes now! -- been higher and their yields -- especially for large die -- lower, and their tested good die cost higher still because of both factors combined.

All of which is fine when you're an IDM selling CPUs protected against open competition by an x86 IP firewall, but not so fine when you're a foundry selling chips on the open market in direct competition with TSMC, and your customers can see your yield data... :-(
 
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Yes Intel has done large dies, but that still doesn't mean they had yield comparable with TSMC on them -- when you're an IDM selling a high-end HPC CPU for $10000 it doesn't matter so much if the yield is lower because this is hidden from your customers, there's no direct competition, and your overall product margin and profit is still massive.
Even after like the process is super mature? Like Intel 7
Everything I've ever heard from people who actually know about real Intel yield and wafer costs says that compared to TSMC their wafer costs have always -- over many process nodes now! -- been higher and their yields -- especially for large die -- lower, and their tested good die cost higher still because of both factors combined.
I agree with that Intel actually never paid much attention to their cost structure until they started foundry. I would say their yield would still be pretty good may be not at TSMC level good but the cost structure sucks for all recent nodes in HVM.
All of which is fine when you're an IDM selling CPUs protected against open competition by an x86 IP firewall, but not so fine when you're a foundry selling chips on the open market in direct competition with TSMC, and your customers can see your yield data... :-(
Yeah
 
Even after like the process is super mature? Like Intel 7

I agree with that Intel actually never paid much attention to their cost structure until they started foundry. I would say their yield would still be pretty good may be not at TSMC level good but the cost structure sucks for all recent nodes in HVM.

Yeah
Regardless of how mature the process is, if Intel yield never catches up with TSMC (and neither does their wafer cost) their die cost will always be higher, even if both drop with time as yield improves.

Wafer cost is higher in recent nodes (and still increasing each new node) due to more complex and expensive masks and process steps, but TSMC get round this by putting up the wafer selling price -- cost per transistor has pretty much flattened off, so if the next node is (for example) 20% denser it costs (for example) 20% more at the same stage in process maturity. But if you need the higher density and lower power for your next product, you really don't have much choice -- it's a case of sh*t or get off the pot... :-(

If you have to ask how much an N2 mask set/wafers cost (21 metal layers!!!), you probably can't afford it... ;-)
 
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