Nova Lake to use TSMC N2P for all but Entry Configuration According to Moore's Law is Dead

[siliconbruh999]

Intel hasn't shown industry-leading innovation in chip design since they made the Pentium superscalar. Itanium, as misguided as it was, was designed by HP. Most of Intel's so-called leadership designs were barely competitive, often trailing, but achieved leadership due to a one or two generation fab process advantage. I think it's time Intel let the chip design innovation proceed. It's been a long time since that's been the case.

I beg to disagree Core was Industry leading architecture after that there were minimal improvements also the atom team is doing quite innovative work that is not getting looked upon they are doing x86 without microOP caches they are doing triple cluster decoding

 

[Xebec]

Intel hasn't shown industry-leading innovation in chip design since they made the Pentium superscalar. Itanium, as misguided as it was, was designed by HP. Most of Intel's so-called leadership designs were barely competitive, often trailing, but achieved leadership due to a one or two generation fab process advantage. I think it's time Intel let the chip design innovation proceed. It's been a long time since that's been the case.

I agree with your point, but -- there were quite a few superscalar chips before Pentium -- AMD 29050, Motorola 88K, etc.

On the flip side, Intel had a lot of individual innovations that were ahead of everyone else (the Pentium 4 branch predictor was the most capable x86 BP until 2020's Zen 3 -- https://chipsandcheese.com/p/intels-netburst-failure-is-a-foundation-for-success ). Sandy Bridge on 32nm also crushed AMD chips on 32nm and 22nm, and Core 2 completely flipped the table on power efficiency vs K8 and later K10. Pentium 3 and Pentium M leaped over Transmeta's power efficiency advantages, etc.

I think you're underselling Intel's chip / products innovation a little

 

[blueone]

I beg to disagree Core was Industry leading architecture after that there were minimal improvements also the atom team is doing quite innovative work that is not getting looked upon they are doing x86 without microOP caches they are doing triple cluster decoding

I beg to disagree too. When Core was introduced the memory controller was still in the northbridge, so system-level performance, power consumption, and cost were still worse than comparable AMD processors. Intel didn't fix that architectural brain fart until Nehalem. Lots of senior engineers in the company were pretty disgusted. They weren't willing to give up the revenue from selling memory controller chipsets (which was something like $5B/year, if my internal memory controller is still working, which was real money back then, and high margin too because Intel put chipsets on the depreciated N-1 process. More than enough to build an N-process fab.

I was never an Atom fan. X86 is not the right architecture or instruction set for real power efficiency. It was an instance of "the only tool we have is a hammer, so everything has to be considered a nail".

 

[siliconbruh999]

I was never an Atom fan. X86 is not the right architecture or instruction set for real power efficiency. It was an instance of "the only tool we have is a hammer, so everything has to be considered a nail".

Well the Unified Core is based on Atom that is replacing future P cores and atom has evolved in a. Nice way.
As for x86 the only problem I see is Intel's and AMD trying to make 6-7 GHz clocking architecture instead of increasing IPC.

 

[blueone]

Well the Unified Core is based on Atom that is replacing future P cores and atom has evolved in a. Nice way.

I didn't know that.

As for x86 the only problem I see is Intel's and AMD trying to make 6-7 GHz clocking architecture instead of increasing IPC.

As for increasing IPC in x86 instruction processing, when I discussed that with a few friends who were CPU architects years ago (I'm not one), I was told that x86 instruction processing made wider designs (e.g. more decode and execution pipelines) die area and power consumption problems. I heard that turning up the clock speed was far cheaper and easier, though those were the days of substantial fab process leadership. I'd love to be a fly on the wall in those conversations now...

 

[siliconbruh999]

As for increasing IPC in x86 instruction processing, when I discussed that with a few friends who were CPU architects years ago (I'm not one), I was told that x86 instruction processing made wider designs (e.g. more decode and execution pipelines) die area and power consumption problems. I heard that turning up the clock speed was far cheaper and easier, though those were the days of substantial fab process leadership. I'd love to be a fly on the wall in those conversations now...

Yeah same but that problem has been solved with clustered decoding not to mention Intel APX as an extension finally matching ARM in architectural register count that would provide some IPC boost.

Introducing Intel® Advanced Performance Extensions (Intel® APX)

These extensions expand the x86 instruction set with access to registers and features that improve performance.

www.intel.com

 

[blueone]

Yeah same but that problem has been solved with clustered decoding not to mention Intel APX as an extension finally matching ARM in architectural register count that would provide some IPC boost.

Introducing Intel® Advanced Performance Extensions (Intel® APX)

These extensions expand the x86 instruction set with access to registers and features that improve performance.

www.intel.com

View attachment 3476

I know about APX, but I thought the idea was to make an application's object code more efficient so it ran faster, not that APX would impact IPC.

 

[siliconbruh999]

I know about APX, but I thought the idea was to make an application's object code more efficient so it ran faster, not that APX would impact IPC.

It would more register even though register are renamed during OOO the results have to be written to physical registers and when the registers are bottleneck not to mention load and store are bottleneck in the code it wold affect the results

Performance Speed Limits

A laundry list of speed limits that your code can’t exceed.

travisdowns.github.io

 

[Xebec]

I beg to disagree too. When Core was introduced the memory controller was still in the northbridge, so system-level performance, power consumption, and cost were still worse than comparable AMD processors. Intel didn't fix that architectural brain fart until Nahalem. Lots of senior engineers in the company were pretty disgusted. They weren't willing to give up the revenue from selling memory controller chipsets (which was something like $5B/year, if my internal memory controller is still working, which was real money back then, and high margin too because Intel put chipsets on the depreciated N-1 process. More than enough to build an N-process fab.

I was never an Atom fan. X86 is not the right architecture or instruction set for real power efficiency. It was an instance of "the only tool we have is a hammer, so everything has to be considered a nail".

I thought it was silly Intel didn't do IMC with C2, but, Core 2 sticking with the FSB had two advantages:

- Nvidia nForce chipset gave Intel buyers a decent onboard GPU option when AMD had no such thing (this was pre-Llano)
- The later Pentium 4/D boards could be upgraded to Core 2 Duo/Quad. Quite an upgrade path.

On efficiency, Core 2 did tend to idle a little higher than Athlon K8 on desktop, but under load Core 2 was significantly more efficient, due to much higher performance. (Below compares the "Extreme" Intel chip to the "Energy Efficient" K8 SKUs):

The bottom line is that Intel just gets it done faster while pulling fewer watts (e.g. Performance/Watt on the X6800 is 0.3575 vs. 0.2757 on the X2 3800+ EE SFF). (Source: https://web.archive.org/web/20240518100225/https://www.anandtech.com/show/2045/7 )

..

That said, that's really interesting internal "fighting" caused Core 2 to not get an IMC..

I did like AMD's Cat cores fwiw.

 

[Xebec]

P.S. Here's "blueone" in the Pentium-M Days

 

[Sølve Folkestad Dahl]

Also, MLID is a liar, so it's best not to believe any information from Intel.

From having observed him for some years I'd venture that most of his content is... original (made up).

 

[tomatoma]

I beg to disagree too. When Core was introduced the memory controller was still in the northbridge, so system-level performance, power consumption, and cost were still worse than comparable AMD processors. Intel didn't fix that architectural brain fart until Nahalem. Lots of senior engineers in the company were pretty disgusted. They weren't willing to give up the revenue from selling memory controller chipsets (which was something like $5B/year, if my internal memory controller is still working, which was real money back then, and high margin too because Intel put chipsets on the depreciated N-1 process. More than enough to build an N-process fab.

I was never an Atom fan. X86 is not the right architecture or instruction set for real power efficiency. It was an instance of "the only tool we have is a hammer, so everything has to be considered a nail".

Personally, I think ISA has nothing to do with it.
The biggest difference is the difference in microarchitecture.
It can be said that the X86 group has little experience in designing ultra-low power consumption.

 

[lefty]

MLID has had a few good leaks, but also quite a few misses. Take this with a really big grain of salt.

He was wildly overoptimistic on Meteor Lake, Arrow Lake, and Zen 5. He is currently suggesting Zen 6 is aiming for 7 GHz (though he said he expects at least 6.4 GHz), and "double digit IPC increases over Zen 5", so I guess we'll see next year.

Also, Nova Lake on N2P doesn't necessarily mean 18A isn't performing or yielding at all, it could just mean that N2 is more cost effective overall. (scale + yields). Intel may also need TSMC packaging for what they're planning.

(P.S. I am personally disappointed if this comes out as a mainly N2P product. I would have liked to have seen 18A do something really good for desktop..)

This reminds me of Cannonlake. You had these white papers promising incredible performance and fancy process features like cobalt interconnects, but the reality is they only released one solitary SKU (the Core i3-8121U).
Flash forward to today... we have white papers promising incredible performance and fancy process features like back side power delivery... and only one single Nova SKU released, the entry level 4 core version...

 

[Xebec]

This reminds me of Cannonlake. You had these white papers promising incredible performance and fancy process features like cobalt interconnects, but the reality is they only released one solitary SKU (the Core i3-8121U).
Flash forward to today... we have white papers promising incredible performance and fancy process features like back side power delivery... and only one single Nova SKU released, the entry level 4 core version...

I agree that is has that feeling.. though there's always some chance they'll pull a rabbit out of the hat.

I remember an article (unable to find it) that at one point, Intel talked about "if 22nm is too hard, we'll do 3-4 steps, 29nm, 27nm, 25nm, then 22nm" or something similar. Of course nm was meaningless, but they were hinting that they weren't confident in 22nm being a timely step after 32nm, yet still succeeded.

 

[eding42]

I agree that is has that feeling.. though there's always some chance they'll pull a rabbit out of the hat.

I remember an article (unable to find it) that at one point, Intel talked about "if 22nm is too hard, we'll do 3-4 steps, 29nm, 27nm, 25nm, then 22nm" or something similar. Of course nm was meaningless, but they were hinting that they weren't confident in 22nm being a timely step after 32nm, yet still succeeded.

This would be true if Intel wasn't scheduled to launch Panther Lake a year before Nova Lake. As I've said a few times before, if this is a truly Cannon Lake situation we will know in 3-4 months when PTL launches / doesn't launch. 18a by H2/2026 should be relatively mature. I heard rumors that the plan was to use 18a/p for NVL, maybe the 18a/p is delayed?

Maybe 18a has lower Fmax than N2P and Zen 6 clocks particularly well (though I doubt 7 GHz LOL). Understandable that Intel might not tolerate even a 200-300 Mhz clock deficit vs. Zen 6, when Coyote Cove seems to be a normal (not exceptional) IPC bump. It's about which one you prioritize - Intel Foundry financials or an extra 5-10% ST vs AMD?

 

[blueone]

I thought it was silly Intel didn't do IMC with C2, but, Core 2 sticking with the FSB had two advantages:

- Nvidia nForce chipset gave Intel buyers a decent onboard GPU option when AMD had no such thing (this was pre-Llano)
- The later Pentium 4/D boards could be upgraded to Core 2 Duo/Quad. Quite an upgrade path.

On efficiency, Core 2 did tend to idle a little higher than Athlon K8 on desktop, but under load Core 2 was significantly more efficient, due to much higher performance. (Below compares the "Extreme" Intel chip to the "Energy Efficient" K8 SKUs):

The bottom line is that Intel just gets it done faster while pulling fewer watts (e.g. Performance/Watt on the X6800 is 0.3575 vs. 0.2757 on the X2 3800+ EE SFF). (Source: https://web.archive.org/web/20240518100225/https://www.anandtech.com/show/2045/7 )

FSB had no technical advantages at all. It was a braindead design when it was introduced. It was just cheap and simple to implement.

That said, that's really interesting internal "fighting" caused Core 2 to not get an IMC..

I did like AMD's Cat cores fwiw.

I'm sorry for my obtuse wording in the earlier post. To clarify, the people who wanted to keep the northbridge discrete were senior executives who wanted to maintain northbridge revenue. Every engineer I ever spoke to always thought the same way I did - the memory controller should be integrated with the CPU for lower latency, higher throughput, lower system power, and lower cost. Waiting until Nehalem was profoundly dumb.

 

[siliconbruh999]

I want Lip Bu tan to fire people making these decisions they don't deserve the jobs man they just are a barrier to technology improvement

 

[count]

I am a manufacturing guy with 20 years experience in advanced manufacturing.

I am looking at back side power delivery from a manufacturing standpoint.... to me it looks like a genius design from a product standpoint, but a huge challenge to manufacture, since you basically have to shave off the back of the die at micron accuracy, and then align the interconnect at sub micron accuracy, and it still has to happen at a reasonably high throughput. The cherry on top is this all has to be done with incredibly fragile workpieces where the slightest bit of contamination will ruin the die.

Manufacturing problems with this many layers of complexity often take many many years to work out.

 

[Xebec]

FSB had no technical advantages at all. It was a braindead design when it was introduced. It was just cheap and simple to implement.

I'm sorry for my obtuse wording in the earlier post. To clarify, the people who wanted to keep the northbridge discrete were senior executives who wanted to maintain northbridge revenue. Every engineer I ever spoke to always thought the same way I did - the memory controller should be integrated with the CPU for lower latency, higher throughput, lower system power, and lower cost. Waiting until Nehalem was profoundly dumb.

OT - but would you consider Nehalem its own architecture or really just Conroe+ with IMC?

Sandy bridge felt like a major uarch change but I was never clear on Nehalem.

 

[MKWVentures]

Intel products group likes working with TSMC, They are easy to work with and they provide capacity options that IFS does not. Plus there is a reasons why TSMC and their customers want and non-BSPD process.