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Hello everyone,
Why was TSMC able to surpass Intel and become the world’s most advanced semiconductor manufacturer?
Many would give the simple and familiar answers: the foundry business model, Intel’s complacency, and so on.
But the outcome of such a long-term technological war is really the sum of many smaller battles.
A recent interview with TSMC Executive VP and co-COO Y.J. Mii（米玉傑）, newly elected as an ITRI Fellow, reveals one of the company’s long-kept tactical secrets.
Now the undisputed leader of the global semiconductor industry, TSMC has become increasingly guarded in its dealings with the media in recent years.
Caught in the crossfire of U.S.–China geopolitical tensions, its senior executives seldom grant interviews—let alone speak candidly about corporate strategy or technology.
That’s why the semi-official interview with newly appointed Executive Vice President and Co-Chief Operating Officer Y.J. Mii, published in the Industrial Technology and Information monthly journal after his election as an ITRI Fellow, felt especially rare — and, to me, like a real treasure.
In the interview, Mii—who for years co-led TSMC’s vast R&D organization alongside the recently retired Wei-Jen Lo（羅唯仁）—was credited with one of the company’s most influential innovations: the “half-node.” Introduced in the 1990s, it was described as “a uniquely TSMC model of customer service.”
What Exactly Is a “Half-Node”?
This lesser-known yet crucial strategy has long been one of TSMC’s hidden advantages.
To understand it, we first need to recall what a “full-node” shrink means.
Essentially, it follows the logic of Moore’s Law—every 18 to 24 months, the area of a transistor is reduced by half, corresponding to roughly a 0.7× reduction in its linear dimensions.
The industry progressed in an orderly fashion from 90 nm to 65 nm to 45 nm, and so on. This systematic scaling—long led by Intel—became known as the full-node shrink.
But TSMC often played by different rules. In 2007, for instance, its 55 nm process arrived between 65 nm and 45 nm—a half-node that shrank dimensions by only about 10 percent.
As Mii explained in the interview, the 55 nm generation reused much of the 65 nm process technology.
“By shrinking dimensions through lithography while retaining the same design foundations, only minor adjustments were needed to maintain compatibility with existing device libraries and IP. Because the design rules were linearly scaled, customers could save considerable redesign time,” explained Y.J. Mii in Industrial Technology and Information.
How was this possible?
In the early stages of any new process ramp, risks are high. TSMC takes a cautious approach by setting a wider process-window tolerance—allowing for greater variability in design and manufacturing.
As production matures and experience accumulates, that window can be tightened, enabling finer and more precise process control.
“Mii and his team would take each matured generation and execute an additional shrink on the same production equipment—delivering fresher, more efficient technologies that customers embraced enthusiastically. This approach propelled TSMC ahead of competitors and cemented its leadership position.” according to Industrial Technology and Information.
The Battle of 28 nm: Morris Chang’s Proudest Victory
The story recalls one of my most memorable interviews—with TSMC founder Morris Chang（張忠謀） in 2016.
Known for discussing grand strategy and global trends, Chang that day reflected instead on a concrete business battle—his proudest triumph: the 28 nm era.
“Later generations, like 16 nm, were good,” Chang said. “But none were as successful as 28 nm.”
At the time, I asked why TSMC’s 28 nm process—already six years old—still retained nearly 80 percent of the market, far ahead of Samsung and GlobalFoundries.
With a wry smile, Chang joked that he deserved a medal.
While its rivals struggled to ramp up 28 nm production, TSMC succeeded with one decisive advantage. After that victory, Chang repeatedly reminded his senior executives every month not to let their guard down—and to “press the advantage.”
And how did they do that? Through the half-node approach—specifically, four consecutive half-nodes.
For the smartphone SoC market, TSMC rolled out four successive versions of its 28 nm process, refreshing it almost yearly and leaving competitors perpetually behind.
The 28HPC+ process, introduced in 2015, shrank transistor dimensions by an additional 4 percent, boosted performance, and cut power consumption by 30 percent compared with the previous version.
As one foreign analyst noted:
“Smartphones launch a new generation every year. TSMC’s half-nodes gave customers something new to adopt annually.”
That philosophy still defines TSMC’s strategy today. Some of its half-nodes are now rebranded as entirely new numbers—for example, Nvidia’s H100 and GB200 chips are built on TSMC’s 4 nm process, which in fact belongs to the 5 nm family.
Within that family alone are multiple variants: N5, N5P, N4P, N4C, N4X (optimized for high-performance computing), and N5A (for automotive).
Likewise, 12 nm and 6 nm are half-node extensions of the 16 nm and 7 nm generations, respectively.
Analysts view this as the clearest embodiment of TSMC’s “small-step, fast-run” R&D philosophy.
Even today, much of the industry still follows the full-node scaling model rooted in Moore’s Law—a tradition that began with Intel.
Intel’s “Tick-Tock” vs. TSMC’s “Small-Step” Stability
Intel’s famed “Tick-Tock” strategy—alternating annual updates to process and architecture—produced a full-node advance every two years.
“That’s a big leap to make in one step,” an analyst explained. “TSMC, by contrast, takes smaller steps—but ensures each one lands firmly.”
The operative word, he added, is stability.
TSMC’s approach to new technologies is cautious: whether GAA transistors, backside power delivery, or High-NA EUV, the company rarely rushes to adopt first.
“Let others try to take the corner first,” the analyst said. “They’re often the ones who crash.”
Behind TSMC’s ability to sustain so many viable half-nodes lies its vast ecosystem—over 500 customers, thousands of products each year, and tens of thousands of R&D engineers—creating unmatched scale and feedback loops.
What began as a “small-step” innovation has now become an industry standard.
The “Number Game” Among Foundries
Samsung has perhaps taken the idea even further—sometimes to the point of numerical confusion.
Within its so-called 5 nm family, versions labeled “N4” or even “N3” blur the line between half- and full-nodes.
Recently, Korean media reported that Samsung’s upcoming “2 nm” process—touted as a potential leapfrog over TSMC—may in fact be another “3 nm half-node.”
TSMC itself once played a similar game when trailing Intel. Both companies recognized 65 nm as a full node, but while Intel’s next step was 45 nm, TSMC jumped to 40 nm.
Strategically, that move was brilliant: if TSMC lagged Intel by a year, then when TSMC’s 40 nm launched, Intel’s 45 nm still had another year before its 32 nm successor appeared.
To the outside world, it looked as though TSMC had pulled ahead. “For half that cycle, we looked like the leader,” recalled a former TSMC executive.
That generation marked a turning point. “From then on, TSMC led the foundry industry in redefining what counts as a main node versus a half-node,” said one veteran analyst. “Volume defines leadership.”
Indeed, when TSMC’s 28 nm became dominant, Intel executives dismissed it as a mere half-node.
But Samsung, GlobalFoundries, and UMC all followed TSMC’s lead—cementing 28 nm as the de facto global standard.
The Judgment That Let TSMC Surpass Intel
Back to Y.J. Mii. Despite earning a PhD in electrical engineering from UCLA and starting his career as a research engineer at IBM, few know that his first role at TSMC wasn’t in R&D but in manufacturing—as a process-integration engineer at Fab 3, where he eventually became deputy fab manager before moving to R&D.
A former colleague recalled that, in those days, R&D teams often produced technologies difficult to mass-produce. Then-VP Rick Tsai（蔡力行） reassigned Mii to oversee pilot production lines to ensure manufacturability of new processes.
That dual exposure shaped Mii’s hallmark decision years later. While leading development of the 7 nm process, he judged that EUV lithography was still not mature enough for volume production—so he insisted that the first generation rely on multi-patterning, introducing EUV only in the second generation.
The result was a resounding success—the process that allowed TSMC to surpass Intel.
That judgment reflected Mii’s rare experience bridging both manufacturing and R&D.
“Cross-organizational collaboration is TSMC’s greatest strength,” said a long-time company veteran. “You could call it the most important internal capability—and the real key to its success.”
cwnewsroom.substack.com
Hello everyone,
Why was TSMC able to surpass Intel and become the world’s most advanced semiconductor manufacturer?
Many would give the simple and familiar answers: the foundry business model, Intel’s complacency, and so on.
But the outcome of such a long-term technological war is really the sum of many smaller battles.
A recent interview with TSMC Executive VP and co-COO Y.J. Mii（米玉傑）, newly elected as an ITRI Fellow, reveals one of the company’s long-kept tactical secrets.
Now the undisputed leader of the global semiconductor industry, TSMC has become increasingly guarded in its dealings with the media in recent years.
Caught in the crossfire of U.S.–China geopolitical tensions, its senior executives seldom grant interviews—let alone speak candidly about corporate strategy or technology.
That’s why the semi-official interview with newly appointed Executive Vice President and Co-Chief Operating Officer Y.J. Mii, published in the Industrial Technology and Information monthly journal after his election as an ITRI Fellow, felt especially rare — and, to me, like a real treasure.
In the interview, Mii—who for years co-led TSMC’s vast R&D organization alongside the recently retired Wei-Jen Lo（羅唯仁）—was credited with one of the company’s most influential innovations: the “half-node.” Introduced in the 1990s, it was described as “a uniquely TSMC model of customer service.”
What Exactly Is a “Half-Node”?
This lesser-known yet crucial strategy has long been one of TSMC’s hidden advantages.
To understand it, we first need to recall what a “full-node” shrink means.
Essentially, it follows the logic of Moore’s Law—every 18 to 24 months, the area of a transistor is reduced by half, corresponding to roughly a 0.7× reduction in its linear dimensions.
The industry progressed in an orderly fashion from 90 nm to 65 nm to 45 nm, and so on. This systematic scaling—long led by Intel—became known as the full-node shrink.
But TSMC often played by different rules. In 2007, for instance, its 55 nm process arrived between 65 nm and 45 nm—a half-node that shrank dimensions by only about 10 percent.
As Mii explained in the interview, the 55 nm generation reused much of the 65 nm process technology.
“By shrinking dimensions through lithography while retaining the same design foundations, only minor adjustments were needed to maintain compatibility with existing device libraries and IP. Because the design rules were linearly scaled, customers could save considerable redesign time,” explained Y.J. Mii in Industrial Technology and Information.
How was this possible?
In the early stages of any new process ramp, risks are high. TSMC takes a cautious approach by setting a wider process-window tolerance—allowing for greater variability in design and manufacturing.
As production matures and experience accumulates, that window can be tightened, enabling finer and more precise process control.
“Mii and his team would take each matured generation and execute an additional shrink on the same production equipment—delivering fresher, more efficient technologies that customers embraced enthusiastically. This approach propelled TSMC ahead of competitors and cemented its leadership position.” according to Industrial Technology and Information.
The Battle of 28 nm: Morris Chang’s Proudest Victory
The story recalls one of my most memorable interviews—with TSMC founder Morris Chang（張忠謀） in 2016.
Known for discussing grand strategy and global trends, Chang that day reflected instead on a concrete business battle—his proudest triumph: the 28 nm era.
“Later generations, like 16 nm, were good,” Chang said. “But none were as successful as 28 nm.”
At the time, I asked why TSMC’s 28 nm process—already six years old—still retained nearly 80 percent of the market, far ahead of Samsung and GlobalFoundries.
With a wry smile, Chang joked that he deserved a medal.
While its rivals struggled to ramp up 28 nm production, TSMC succeeded with one decisive advantage. After that victory, Chang repeatedly reminded his senior executives every month not to let their guard down—and to “press the advantage.”
And how did they do that? Through the half-node approach—specifically, four consecutive half-nodes.
For the smartphone SoC market, TSMC rolled out four successive versions of its 28 nm process, refreshing it almost yearly and leaving competitors perpetually behind.
The 28HPC+ process, introduced in 2015, shrank transistor dimensions by an additional 4 percent, boosted performance, and cut power consumption by 30 percent compared with the previous version.
As one foreign analyst noted:
“Smartphones launch a new generation every year. TSMC’s half-nodes gave customers something new to adopt annually.”
That philosophy still defines TSMC’s strategy today. Some of its half-nodes are now rebranded as entirely new numbers—for example, Nvidia’s H100 and GB200 chips are built on TSMC’s 4 nm process, which in fact belongs to the 5 nm family.
Within that family alone are multiple variants: N5, N5P, N4P, N4C, N4X (optimized for high-performance computing), and N5A (for automotive).
Likewise, 12 nm and 6 nm are half-node extensions of the 16 nm and 7 nm generations, respectively.
Analysts view this as the clearest embodiment of TSMC’s “small-step, fast-run” R&D philosophy.
Even today, much of the industry still follows the full-node scaling model rooted in Moore’s Law—a tradition that began with Intel.
Intel’s “Tick-Tock” vs. TSMC’s “Small-Step” Stability
Intel’s famed “Tick-Tock” strategy—alternating annual updates to process and architecture—produced a full-node advance every two years.
“That’s a big leap to make in one step,” an analyst explained. “TSMC, by contrast, takes smaller steps—but ensures each one lands firmly.”
The operative word, he added, is stability.
TSMC’s approach to new technologies is cautious: whether GAA transistors, backside power delivery, or High-NA EUV, the company rarely rushes to adopt first.
“Let others try to take the corner first,” the analyst said. “They’re often the ones who crash.”
Behind TSMC’s ability to sustain so many viable half-nodes lies its vast ecosystem—over 500 customers, thousands of products each year, and tens of thousands of R&D engineers—creating unmatched scale and feedback loops.
What began as a “small-step” innovation has now become an industry standard.
The “Number Game” Among Foundries
Samsung has perhaps taken the idea even further—sometimes to the point of numerical confusion.
Within its so-called 5 nm family, versions labeled “N4” or even “N3” blur the line between half- and full-nodes.
Recently, Korean media reported that Samsung’s upcoming “2 nm” process—touted as a potential leapfrog over TSMC—may in fact be another “3 nm half-node.”
TSMC itself once played a similar game when trailing Intel. Both companies recognized 65 nm as a full node, but while Intel’s next step was 45 nm, TSMC jumped to 40 nm.
Strategically, that move was brilliant: if TSMC lagged Intel by a year, then when TSMC’s 40 nm launched, Intel’s 45 nm still had another year before its 32 nm successor appeared.
To the outside world, it looked as though TSMC had pulled ahead. “For half that cycle, we looked like the leader,” recalled a former TSMC executive.
That generation marked a turning point. “From then on, TSMC led the foundry industry in redefining what counts as a main node versus a half-node,” said one veteran analyst. “Volume defines leadership.”
Indeed, when TSMC’s 28 nm became dominant, Intel executives dismissed it as a mere half-node.
But Samsung, GlobalFoundries, and UMC all followed TSMC’s lead—cementing 28 nm as the de facto global standard.
The Judgment That Let TSMC Surpass Intel
Back to Y.J. Mii. Despite earning a PhD in electrical engineering from UCLA and starting his career as a research engineer at IBM, few know that his first role at TSMC wasn’t in R&D but in manufacturing—as a process-integration engineer at Fab 3, where he eventually became deputy fab manager before moving to R&D.
A former colleague recalled that, in those days, R&D teams often produced technologies difficult to mass-produce. Then-VP Rick Tsai（蔡力行） reassigned Mii to oversee pilot production lines to ensure manufacturability of new processes.
That dual exposure shaped Mii’s hallmark decision years later. While leading development of the 7 nm process, he judged that EUV lithography was still not mature enough for volume production—so he insisted that the first generation rely on multi-patterning, introducing EUV only in the second generation.
The result was a resounding success—the process that allowed TSMC to surpass Intel.
That judgment reflected Mii’s rare experience bridging both manufacturing and R&D.
“Cross-organizational collaboration is TSMC’s greatest strength,” said a long-time company veteran. “You could call it the most important internal capability—and the real key to its success.”
Not Just Numbers: How TSMC’s “Small-Step, Fast-Run” Strategy Became Its Secret Weapon Against Samsung and Intel
Liang-rong Chen
cwnewsroom.substack.com
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