It’s official: High-NA EUV will get a successor
- Thread starter Daniel Nenni
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Full EUV was 2020 with TSMC N5 but I guess you could claim N7+ in 2019.
When will Intel have HNA-EUV chiplets? TSMC needs to do full chip so my guess is 2028.
hist78
Well-known member
Or, 2036 for the High NA EUV HVM, using the 12 years difference between IMEC R&D and industry adoption from the EUV deployment history.
And N2 is pretty much N3 with HNS transistors replacing FinFETs, the basic pitches (metal and contacted poly) hardly changed. That's three headline process generations (N3/N2/A16) with almost identical underlying technology...
If you want another example of how marketing has taken over the process circus, look at actual physical gate length instead on the headline "Xnm" number -- this has been static at around 16nm for many Finfet generations all the way down to the last one (N3), in spite of what is drawn or labelled. Even switching to HNS for N2/A16 and similar (and future HNS processes) this only drops to about 13nm, and CPP and MP have pretty much stalled...
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That is the key observation. Channel control is limited by end effects which bottom out at 16nm for fins, 13nm for ribbons, using Si. There are indications that W/Mo S2 2-D materials could go down to 10nm with adequate control but those are not even on roadmap, and who knows if they will solve the problem of building source/drain contacts in a compact way.
The 13nm ribbon length comes with a 4th side so capacitance/nm goes up, meaning the CV^2/2 switching energy is not moving. Increased perfection in materials may deliver some Ceff reduction, but overall we have been near perfection for a silicon channel for a while.
Functions like matmul which dominate AI will reach power densities that cannot be cooled if they shrink without solving C and V.
Right. And please look at the date of J.P. publication by IanD. I remember seeing his presentation at IEDM 1990 where GAA was already there and some of his early 2000s papers on advantages and disadvantages of various device structures. Unfortunately marketing took over
Issues with 2D materials will require a lot of work before they can be introduced. Even assuming a good fabrication method for them is found, the physical issues of making low resistance contacts between a 2D semiconductor and a 3D metal or semiconductor is always there let alone its size. It can easily be the limiting factor compared to CV^2/2. Plus its topology will not be much different than HNS or CFET variants so same issues in litho. No magic bullets.
Issues with 2D materials will require a lot of work before they can be introduced. Even assuming a good fabrication method for them is found, the physical issues of making low resistance contacts between a 2D semiconductor and a 3D metal or semiconductor is always there let alone its size. It can easily be the limiting factor compared to CV^2/2. Plus its topology will not be much different than HNS or CFET variants so same issues in litho. No magic bullets.
My bet is on going cold, with device materials engineered for low voltage thresholds. I don't see it shrinking devices but it will allow more work done with less power:
From that same interview:
As time advances technology improves. Remember when folks said there was no economic way to continue scaling because of the end of Dennard scaling, because 248nm hit the resolution limit, or not having EUV by 45nm would doom us since 193nm dry hit it's limit at 65nm nodes. The chip makers and tool vendors make the impossible possible.
Also having lead customers helps:
If there is demand from chip makers than ASML will find a way to make it happen (although let's hope "the way" is faster than the 30 or so years that low-NA EUV needed
This would be my take as well. I'm planning an article detailing how far ASML believes it can take dimensional scaling cost-effectively.
I should note that I initially worded the title of the article quoted in the opening post too strongly, and it has been updated accordingly. I don't think ASML/Van den Brink would be talking publicly about hyper-NA if development wasn't far along, though. My guess is they're dotting the i's.
I suspect they anticipate High-NA performance won't be so great, need a next step. The interception is close to original projected HVM of High-NA.
Will you discuss electrons in your article?
That sounds more like an Imec thing. But isn't it always the case that certain requirements seem unattainable early on, only to be met eventually anyhow?
No. It will be an enormous effort that cannot be hidden, which is why they need to talk about it. Shareholders must be aware.
Dotting the i's is where High NA hopes it is now. Like MOx resists thought they were 2 years ago... and they are still dotting them.
Except for the additional power (and space and cost and complexity) needed to keep things cold, which in reality is likely to be bigger than the chip power saved by running cold especially for small systems/solutions...My bet is on going cold, with device materials engineered for low voltage thresholds. I don't see it shrinking devices but it will allow more work done with less power:
(yes I read the paper you linked to, and it kind of ignores the realities of what is needed to run stuff at LN2 temperatures in the real world as opposed to the lab -- not just efficiency but cost/size which doesn't scale down)
TSMC did not say that, Kevin did, and he was in hot water for it.
I was there, he said it in a press lunch not during his Symposium presentation. It was off the cuff, not scripted, we were peppering him with HNA-EUV questions. His not liking the sticker price comment was his personal opinion. I have not heard anyone else at TSMC say that. They would also not say officially that HNA-EUV does not work or has technical issues which it most certainly does. TSMC does not want to piss off ASML.
Seeing it in person and reading it is two different things. Tone, body language, context matters.
Oh I'm not saying it does not pose difficulties. It will take a while. But LN2 chilling is already scaled, so the main problems are in the silicon and the modularity for maintenance. Networking will be interesting since glass gets brittle. I expect reliability to be quite high, as has been the pattern for improved cooling in servers at less extreme temps. The main factors appear to be stable temps and elimination of corrosion.
What are these issues for HNA?
The depth of focus is reduced to a third of that for the 0.33NA system. Thus, resists have to be thinner, leading to less absorption, more noise.
The exposure field is halved compared to the 26 mm x 33 mm standard. Large chips need to be stitched together, where not necessary previously.