Is Intel 10nm really denser than TSMC 7nm?

[raghu78]

Interesting. Do the slides have a date? Was it before 6nm was officially announced (May 2019) ? TSMC 7+ is obsolete now that TSMC 6nm is in play. I'm not sure why AMD would put the effort into 7+ for a small density increase when they can do 5nm or easily migrate 7nm designs to 6nm. I also met with Nvidia and they are still on TSMC 7nm and will migrate to 6nm.

I would really be surprised if AMD and Nvidia do NOT split manufacturing between TSMC and Samsung. Two foundry sources is always better than one and margins are everything for fabless chip companies.

It will be interesting to see what happens at SEMICON West next month. Scott Jones and I will be there and the meeting requests just keep on coming. Intel hired some outsiders for marketing so there are a lot of familiar faces this year.

Daniel TSMC 7+ is already in volume production while N6 will start risk production in Q1 2020, be ready for tapeouts in H2 2020 and volume production is slated for end of 2020. TSMC stated in their earnings call that a few of their customers have taped out on 7+ this year. AMD's Zen 3 is stated to have taped out (from a friend of mine who has sources at AMD) on TSMC 7+ in late Jan 2019. AMD's roadmap also states 7nm+ Zen 3 in 2020. Moreover I think N7+ will have the best PPA compared to the other versions. TSMC has 4 process versions.
1. TSMC N7 DUV (in volume production from Q2 2018) - 1st gen 7nm DUV
2. TSMC N7P DUV (in volume production from Q2 2019) aka 2nd gen 7nm DUV - fully design rule compatible with 1st gen 7nm DUV . >= +5% transistor perf at same power vs N7 DUV

TSMC 7nm HD and HP Cells, 2nd Gen 7nm, And The Snapdragon 855 DTCO

Update and analysis of TSMC 7-nanometer node low-power and high-performance cells, 2nd generation 7nm, and the design technology co-optimization (DTCO) effort that went into the Snapdragon 855 SoC.

fuse.wikichip.org

https://twitter.com/x/status/1145020370761723906

3. TSMC N6 EUV (risk production Q1 2020 and volume production end of 2020) - design rule compatible with 1st gen 7nm DUV. If you want the area shrink you have to retapeout (RTO) the N7 DUV design.
4. TSMC N7+ EUV (in volume production from Q2 2019) . I think this is the highest performing 7nm process from TSMC with the best feature set and will be used by companies who require the highest transistor performance.

TSMC Technologies for Mobile and HPC - Semiwiki

During TSMC 2018 Technology Symposium, Dr. B.J. Woo, TSMC VP of Business Development presented market trends in the area of mobile applications and HPC computing as well as shared TSMC progress in making breakthrough efforts in the technology offerings to serve these two market segments. Both 5G...

semiwiki.com

The N7+ value proposition includes delivering 20% more logic density over N7, 10% lower power at same speed, and additional performance improvements anticipated from the ongoing collaboration with customers .

TSMC's 7nm+ EUV is in production, improves performance by 10%

Despite how young 7nm technologies are, having yet to appear in a single laptop or desktop, they are already superseded by 7nm+.

www.techspot.com

At TSMC’s recent technology forum in Hsinchu, Taiwan, the company's CEO confirmed new details regarding N7+, TSMC’s refined 7nm node employing EUV (extreme ultraviolet) lithography. Most importantly, N7+ chips are already being produced and 7nm production will ramp up by 150% this year to one million total units.

7+ has identical yield rates to N7 and will steadily improve, while also offering a 20% increase to transistor density. There’s also a 10% performance uplift or 15% power efficiency increase.

As for Nvidia using TSMC and Samsung at 7nm they have officially confirmed it.

Update: Nvidia VP Says Next-Gen GPUs Will Be Made by TSMC and Samsung

Nvidia reportedly confirmed that it's partnered with Samsung to manufacture its Ampere GPU, which is expected to launch in 2020 using its 7nm EUVL process.

www.tomshardware.com

Nvidia executive vice president of operations Debora Shoquist said in a statement that “Recent reports are incorrect – NVIDIA’s next-generation GPU will continue to be produced at TSMC. NVIDIA already uses both TSMC and Samsung for manufacturing, and we plan to use both foundries for our next-generation GPU products.

AMD on the other hand is completely on TSMC 7nm and has confirmed the same. Unless AMD face supply constraints they are likely to stick with TSMC 7nm across their product lineup.

 

[raghu78]

Scott Jones and I will be at SEMICON West next week and will meet with Intel. The goal is to get Intel 10nm on the 7nm TSMC Samsung comparison, at their request. The previous numbers say yes Intel 10nm is denser than Samsung and TSMC 7nm but that may have changed.

The question I have is: Where does Wikichip get their data? I don't see any references. It looks like some of it comes from SemiWiki.

Daniel
David Schor is a very well known and respected writer on semiconductor technology. He attends all the industry events like IEDM, HotChips, SEMICON, VLSI, SIGGRAPH (and many more) and other company specific events held by Intel, TSMC, Samsung, AMD and many others. At times the article does not explicitly mention the source but we can find it in the tag in the article title. For instance the latest article on TSMC 7nm HD and HP cells came from the VLSI 2019 paper from TSMC. In some article the source is explicit as in the below one

TSMC Demonstrates A 7nm Arm-Based Chiplet Design for HPC

A look at a high-performance 7nm Arm-based chiplet architecture which was recently presented by TSMC at the 2019 VLSI Symposium.

fuse.wikichip.org

Earlier this month, at the 2019 VLSI Symposium which was held in Kyoto, Japan, TSMC demonstrated their own chiplet design.

 

[Daniel Nenni]

Daniel TSMC 7+ is already in volume production while N6 will start risk production in Q1 2020, be ready for tapeouts in H2 2020 and volume production is slated for end of 2020. TSMC stated in their earnings call that a few of their customers have taped out on 7+ this year. AMD's Zen 3 is stated to have taped out (from a friend of mine who has sources at AMD) on TSMC 7+ in late Jan 2019. AMD's roadmap also states 7nm+ Zen 3 in 2020. Moreover I think N7+ will have the best PPA compared to the other versions. TSMC has 4 process versions.
1. TSMC N7 DUV (in volume production from Q2 2018) - 1st gen 7nm DUV
2. TSMC N7P DUV (in volume production from Q2 2019) aka 2nd gen 7nm DUV - fully design rule compatible with 1st gen 7nm DUV . >= +5% transistor perf at same power vs N7 DUV

TSMC 7nm HD and HP Cells, 2nd Gen 7nm, And The Snapdragon 855 DTCO

Update and analysis of TSMC 7-nanometer node low-power and high-performance cells, 2nd generation 7nm, and the design technology co-optimization (DTCO) effort that went into the Snapdragon 855 SoC.

fuse.wikichip.org

https://twitter.com/x/status/1145020370761723906

3. TSMC N6 EUV (risk production Q1 2020 and volume production end of 2020) - design rule compatible with 1st gen 7nm DUV. If you want the area shrink you have to retapeout (RTO) the N7 DUV design.
4. TSMC N7+ EUV (in volume production from Q2 2019) . I think this is the highest performing 7nm process from TSMC with the best feature set and will be used by companies who require the highest transistor performance.

TSMC Technologies for Mobile and HPC - Semiwiki

During TSMC 2018 Technology Symposium, Dr. B.J. Woo, TSMC VP of Business Development presented market trends in the area of mobile applications and HPC computing as well as shared TSMC progress in making breakthrough efforts in the technology offerings to serve these two market segments. Both 5G...

semiwiki.com

The N7+ value proposition includes delivering 20% more logic density over N7, 10% lower power at same speed, and additional performance improvements anticipated from the ongoing collaboration with customers .

TSMC's 7nm+ EUV is in production, improves performance by 10%

Despite how young 7nm technologies are, having yet to appear in a single laptop or desktop, they are already superseded by 7nm+.

www.techspot.com

At TSMC’s recent technology forum in Hsinchu, Taiwan, the company's CEO confirmed new details regarding N7+, TSMC’s refined 7nm node employing EUV (extreme ultraviolet) lithography. Most importantly, N7+ chips are already being produced and 7nm production will ramp up by 150% this year to one million total units.

7+ has identical yield rates to N7 and will steadily improve, while also offering a 20% increase to transistor density. There’s also a 10% performance uplift or 15% power efficiency increase.

As for Nvidia using TSMC and Samsung at 7nm they have officially confirmed it.

Update: Nvidia VP Says Next-Gen GPUs Will Be Made by TSMC and Samsung

Nvidia reportedly confirmed that it's partnered with Samsung to manufacture its Ampere GPU, which is expected to launch in 2020 using its 7nm EUVL process.

www.tomshardware.com

Nvidia executive vice president of operations Debora Shoquist said in a statement that “Recent reports are incorrect – NVIDIA’s next-generation GPU will continue to be produced at TSMC. NVIDIA already uses both TSMC and Samsung for manufacturing, and we plan to use both foundries for our next-generation GPU products.

AMD on the other hand is completely on TSMC 7nm and has confirmed the same. Unless AMD face supply constraints they are likely to stick with TSMC 7nm across their product lineup.

Very good information, thank you. I was in Hsinchu last week and you are absolutely correct. Qualcomm is also using both TSMC and Samsung 7nm. It is the smart strategy for top tier fabless companies since wafer pricing and availability is critical moving forward. The geopolitical turmoil confirms this as well.

I would be interested to hear your thoughts on the different 3nm strategies of TSMC and Samsung. It seems TSMC is very focused on cost/yield (conservative approach) while Samsung is more focused on being leading edge. We saw this with TSMC at 20nm bringing in double patterning then FinFETs at 16nm. Same with 7N and 7+ with EUV.

Do you think Samsung 3nm GAA will be a commercial success?

 

[raghu78]

Very good information, thank you. I was in Hsinchu last week and you are absolutely correct. Qualcomm is also using both TSMC and Samsung 7nm. It is the smart strategy for top tier fabless companies since wafer pricing and availability is critical moving forward. The geopolitical turmoil confirms this as well.

I would be interested to hear your thoughts on the different 3nm strategies of TSMC and Samsung. It seems TSMC is very focused on cost/yield (conservative approach) while Samsung is more focused on being leading edge. We saw this with TSMC at 20nm bringing in double patterning then FinFETs at 16nm. Same with 7N and 7+ with EUV.

Do you think Samsung 3nm GAA will be a commercial success?

On TSMC's Q2 2019 earnings call they were asked if they are moving to 3nm GAA in response to Samsung's planned 3nm GAA node which is expected to be in volume production in late 2021. TSMC said they have evaluated all transistor device options and in discussion with their customers have made the decision on which transistor device architecture to use. They said they will reveal the details soon.

https://www.tsmc.com/uploadfile/ir/quarterly/2019/2NQYt/E/TSMC%202Q19%20transcript.pdf

page 8

First question, there's been a lot of discussion recently about more competitions from one of your foundry competitors. Could you, C.C., talk a little bit about a roadmap on 5-nanometer and especially your 3-nanometer? One of your competitors is looking to introduce a new transistor structure like gate-all-around. Is this going to stick with the FinFET and 3-nanometer as well? Or if it's also likely to move to a nanosheet or gate-all-around structure? That's my first question.

The first question? First question is 5-nanometer and 3-nanometer. We think our 5-nanometer is very competitive and the first one in the industry in that geometry. And what is the risk production right now and the volume production in the first half in the next year, these continue to be the same situation. And about the 3-nanometer, let me clarify a little bit. We have evaluated all the possible options and come with a very good solution for our customer. We continue to work with our customer to define the spec, to define the approaches and to meet their requirement and I'll update you about our choices next time.

Let me add that, actually, our 5-nanometer is a full-node stride from our 7-nanometer. And our 3-nanometer is another full node stride from our 5-nanometer. This is very different than our competitors' road map. So if you compare their numerical, 3 is probably closer to the 5. Secondly, on the 5-nanometer capacity build -- the second question is 5-nanometer capacity.

page 22

Second follow-up is I'd like to hear TSMC's views on the next-generation architecture of transistor. So how do you see the FinFET and the gate-all-around or to compare that to see the pros and cons of these 2 architectures in 5-nanometer and 3-nanometer? Because it seems that one of your competitors is -- promote GAA aggressively

Yes, we noticed that. And actually we also have evaluated all the options, right, just as what I said. And we look at the pros and cons. And we work with our customer, and we choose the most competitive in terms of performance and cost-wise. So we choose the most competitive approaches. So we work with our customers, actually.

My guess is we could hear TSMC 3nm process details later this year. I am not sure but I think TSMC will move to 3nm GAA with risk production in H1 2021 and volume production in H1 2022. One of the very valid points raised by TSMC on the call was their competitor's 5nm is not a full node jump while their 5nm is. Thats very true. TSMC N5 is expected to have a logic density of roughly 175 MTx / sq mm. Samsung will get to that density only with their 3nm GAA in late 2021 or early 2022.

Samsung Announces 3nm GAA MBCFET PDK, Version 0.1

www.anandtech.com

TSMC also confirmed that their 3nm is a full node jump compared to 5nm. imo TSMC 3nm will arrive just slightly behind Samsung 3nm GAA but be a full node ahead in terms of density. In summary I do not see any threat to TSMC from Samsung. TSMC's leadership position at 7nm and 5nm will probably strengthen even more at 3nm.

Moreover I do no agree that moving to 3nm GAA automatically makes Samsung competitive. PPA, yields, schedule and most importantly customer trust determine success in the foundry business. Samsung made a blunder at 7nm by betting it all on EUV. TSMC is very pragmatic in their technology choices and decision making and that has served them very well.

 

[Daniel Nenni]

raghu78,

From what I understand TSMC 3nm is FinFET and then at 2nm they are going to GAA. TSMC may release a 5/4nm GAA version process after the 3nm FinFET as a first version GAA before the 2nm. This is the cautious TSMC approach that we have all come to know and love. Some call it the Apple approach.

D.A.N.

 

[raghu78]

raghu78,

From what I understand TSMC 3nm is FinFET and then at 2nm they are going to GAA. TSMC may release a 5/4nm GAA version process after the 3nm FinFET as a first version GAA before the 2nm. This is the cautious TSMC approach that we have all come to know and love. Some call it the Apple approach.

D.A.N.

Oh thats interesting news. I am looking forward to TSMC discuss about their 3nm process. TSMC does take a very cautious approach to leading edge semiconductor manufacturing as literally the entire fabless industry depends on them.

 

[count]

I think TSMC's caution will pay off. GAA is a significant change and there is no need to rush. Samsung may be denser, but there will likely be yield, cost, design complexity, and transistor performance tradeoffs to that density. Samsung was denser at 14nm too. Taking a big risk for a small density boost vs the competition is a hail mary strategy that only makes sense if you are behind.

 

[raghu78]

I think TSMC's caution will pay off. GAA is a significant change and there is no need to rush. Samsung may be denser, but there will likely be yield, cost, design complexity, and transistor performance tradeoffs to that density. Samsung was denser at 14nm too. Taking a big risk for a small density boost vs the competition is a hail mary strategy that only makes sense if you are behind.

Samsung 3nm GAA is expected to be roughly the same density as TSMC N5. Samsung 5nm is not a full node jump in terms of density. Its a mild tweak of their 7LPP node which is explained in their recent foundry roadmap presentation and their process specs

Samsung Foundry Update 2019 - Semiwiki

Samsung Foundry recently held their 4th annual technology forum in Santa Clara. This article reviews the highlights of the presentations. There were two prevalent themes throughout – focused execution on the current process roadmap, and the introduction of the 3nm process node features and...

semiwiki.com

TSMC and Samsung 5nm Comparison - Semiwiki

Samsung and TSMC have both made recent disclosures about their 5nm process and I though it would be a good time to look at what we know about them and compare the two processes. A lot of what has been announced about 5nm is in comparison to 7nm so we will first review 7nm. 7nm…

semiwiki.com

Samsung Announces 3nm GAA MBCFET PDK, Version 0.1

www.anandtech.com

Samsung 3nm is expected to have 80% higher density than their 7LPP. TSMC N5 is expected to have 80% higher density than their N7 process. So in terms of density TSMC N5 and Samsung 3nm will be quite similar.