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Is CoWoS-L the reason for the alleged Blackwell delay and is that as much of a problem for TSMC as it is for Nvidia?

Brassmonke

New member
It seems the media have latched on to the notion that the Blackwell delay has all but been confirmed by Nvidia themselves. Analysts seem to quote timelines between 3 weeks and 3 quarters and technical experts (these forums no less) agree that there is a plausible explanation for the issues Blackwell may face in light of the complexities that interconnect/packaging solution of CoWoS-L introduce. I thought the cofounder of Cerebrus put out a fair description of the issue albeit self serving. Would this not impact TSMC as well, if not more so, given their ramp in the new packaging facilities? It certainly doesn't seem like an easy solution and while that hasn't not ever been an impediment to NVDA it does make me wonder if the effective yield on GB200 will be pretty terrible until a better solution than the monolithic B200A comes along.
Why wouldn't NVDA comment on this publicly? Why wouldn't TSMC for that matter?

Given the constraints that Lalama3 already seems to be under on H200, I fail to see how any of the hyperscalers would want anything to do with the 200A. Given that Amazon moved their order from Hopper to Blackwell I really don't see them settling for anything short of the GB200, particularly given that the buildout for a 120KW rack has to be in the works already and throwing a 40kw aircooled chip designed for the Chinese market doesn't make sense.

None of this makes sense to me. What gives?
 
It seems the media have latched on to the notion that the Blackwell delay has all but been confirmed by Nvidia themselves. Analysts seem to quote timelines between 3 weeks and 3 quarters and technical experts (these forums no less) agree that there is a plausible explanation for the issues Blackwell may face in light of the complexities that interconnect/packaging solution of CoWoS-L introduce. I thought the cofounder of Cerebrus put out a fair description of the issue albeit self serving. Would this not impact TSMC as well, if not more so, given their ramp in the new packaging facilities? It certainly doesn't seem like an easy solution and while that hasn't not ever been an impediment to NVDA it does make me wonder if the effective yield on GB200 will be pretty terrible until a better solution than the monolithic B200A comes along.
Why wouldn't NVDA comment on this publicly? Why wouldn't TSMC for that matter?

Given the constraints that Lalama3 already seems to be under on H200, I fail to see how any of the hyperscalers would want anything to do with the 200A. Given that Amazon moved their order from Hopper to Blackwell I really don't see them settling for anything short of the GB200, particularly given that the buildout for a 120KW rack has to be in the works already and throwing a 40kw aircooled chip designed for the Chinese market doesn't make sense.

None of this makes sense to me. What gives?

There is one important consideration for Blackwell's delay. Considering H100 is still in high demand and Nvidia/TSMC still can't fulfill all the orders, what's the rush to release Blackwell as early as possible? A lot of TSMC CoWos quipments are either used on H100 or Blackwell but not both at the same time. It's Nvidia trying to undercut Nvidia if it wants to release Blackwell earlier. There isn't a any powerful competitor right now.

Nvidia released a blowout earnings last night. It will be wise for them to use Blackwell to manage the ever increasing market expectation next year.
 
Blackwell probably delayed longer than Nvidia is letting on. That said, companies will just need to wait longer.

Yes it gives AMD and other would be competitors a little more time to catch up, and maybe provides a small opening, but even if Blackwell is delayed a year I think customers will still be lining up and buying more H100s and H200s in the meantime.
 
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Why wouldn't NVDA comment on this publicly? Why wouldn't TSMC for that matter?
[/QUOTE]

TSMC will never comment on a customer delivery issue. I still have not been able to confirm it. There is a TSMC event coming up here in Silicon Valley. I will know more then.
 
None of this makes sense to me. What gives?
Seems pretty clear what the problem is. Why would fab mask be needed for a CoWaS ?

My guess, there is no room for masking design change in CoWoS-L, and it could be possible to modify the last 1-2 metal layers of chips which are manufactured in frontend fab. Someone said it was due to CTE mismatch and it could make sense for this change.
 
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