By TSMC's metric of at least a 2% PPA improvement counting as a node, TSMC has done 6N4Y (N5P, N4, N4P, N3B, N3E, N3P) during the same period of intel's 5N4Y. By Intel's metric of anything with a greater than 10% PPA improvement counting as a node, TSMC has done 3N4Y (N5 -> N4P, N4P -> N3B, and N3B -> N3P).
By the patent pending Nghanayem metric of "any process with major process flow changes counts as a node" I would call it 2N4Y for TSMC (N3B and N3E with it's completely reworked FEOL process) and 2N4Y (intel 4 and 18A) for intel. If you feel like a PPA amount should also be attached to it, a 1.3-1.5x PPA improvement seems reasonable as the minimum bar to clear. 1.3x PPA is what TSMC touts for N2, and it would feel weird to call anything less "a full process node" even in this day and age. With that said, I don't even know how you could make major process flow changes just to get say a 10% PPA improvement, unless your deliberate goal was to waste money and make changes that didn't even do anything. So I doubt that 1.3-1.5x PPA clause will need to be used very often to call if a process is a full node or not. The only examples that come to mind is when Samsung swapped out their 32/28nm process from a gate first to a RMG process, when TSMC moved their 32/28nm to RMG and canceled their poly Si version because it would have been terrible, and the previously mentioned FEOL rework of N3B to make N3E and sidestep their issues with SAC and self-aligned-gate-endcaps.
