I can think of 4 factors that could be at play.
1) CCG is well known to value performance at all costs. My understanding is they are the sorts of people who will happily pay for that AMG, M series, F sport package, or *insert automobile tuner here* even if it costs double of what the car normally costs.
2) Intel does fully custom internal IPs. These long tail IPs start development 5+ years before products launch. Since Intel products isn't exactly known for fast product development. I think it is a VERY safe assumption that Nova lake and the alleged N2 commitment started development 1-2 years before Intel even made the choice to recommit to internal wafer fabrication. Canceling the N2 version would waste IP development money/time.
3) Once internal manufacturing was back on the menu, continuing to develop in parallel gave a fallback option if 5N4Y looked to be falling on its face since all IPs would already exist on N2. If circa 2023 18A looked like it was progressing poorly you could maybe port to N2 in a timely manner (at least 3 years seems reasonable to go from IPs to final chips out if you really book it. And that lines up with Intel's statement of 3.5 years to go from powerpoint to product on raptor lake). If 18A was fine, well you can just release that small volume product you were already designing to recoup your investment and not bother porting 18A dies to N2.
4) While Intel showed that they could control powervia with their E core test chips running at laptop frequency with matched heat buildup to FSPDN. Maybe for a 1.65V 6.5GHz desktop i9, BSPDN just can't deal with that level of heat even if datacenter and even laptop aren't too problematic. After all, those desktop i9s put out as much heat in a single core as ~2x the temporary boost power of a common full intel laptop chip.
I suspect some combination of the above reasons are why a very small selection of the compute dies are outsourced (assuming the rumors line up with the hinted "sku using some external si"). The only thing I know is that no matter which company we are talking about; choices are rarely made in a vacuum, and they are rarely made for only one reason.
So first. Density is often the biggest part of AC. Intel 14nm oh yeah way more expensive than TSMC 28nm. But it also had almost 4x density so the AC was way way way lower. And when you look at the process for 22nm versus 16FF. Intel had the simpler process than TSMC with similar P&P and slightly worse area! I pick this node in particular because of all the intel vs TSMC technologies, this is closest to a like for like node pre intel 7 vs N7 comparing integration complexity. Something like Intel 14 vs TSMC 16/12 is not a fair cost comparison, since i14 was way better from a PPA perspective. When you compare, say intel 45 vs TSMC 40. Not only did Intel 45 come out years before. But also it was HKMG vs not. That adds cost. But nobody in their right mind would say it was cost ineffective to do HKMG. Another example is when Intel was doing 45 they used dry DUV double patterning while TSMC used immersion single pass litho for theirs to lower cost. But when Intel was doing, their 45 immersion was immature, so you can hardly fault them since at the time that was the cheapest way to do things.
From what I have seen from the prior 2 decades of process technologies, the difference between the best and the rest on wafer cost isn't anywhere near as large as people make it out to be. Take a really good like for like comparison like GF and UMC. UMC is Taiwan based with some Singapore fabs, and they grew up in the same environment as TSMC with very similar process nodes. GF process nodes are from a different lineage and like 1/2 of the manufacturing is in the west. Operating margin between the two historically isn't very far apart. Much of TSMC's margin abnormally high margin is from TSMC's service and reputation, allowing for more premium pricing. Further evidence for that shows up as they left UMC in the dust and then left Samsung and GF in the dust, their GM/OM kept ricing as they became the only choice for leading edge. Now, as good as the "rest", probably not. But people conflate Intel 7 cost ineffective and say all Intel process past and future will all suck as bad as 10nm. Intel says that GM for intel 7 was high single digits and their blend of DUV technologies is 10-20% GM. Considering that Intel 7 at the time was like what 90-95% of DUV wafer shipments. That means 14nm and above would have needed to have a GM of around 19% (assuming worst case of 10% of total volume, that i7 margin is 9%, and blended margin is 11%). 19% isn't really that far removed from the GMs we have been seeing from GF or UMC during the downcycle (20-30% GM and 0-10% OM). Is this to say there is no room for intel to improve. Absolutely not. But much of the structural cost difference are trivial changes or modifications. And based on the relaxed pitches Intel's BSPDN scheme allows, I suspect Scotten's projection of 18A cost being not much higher than N3 and below A16 is correct. Certainly matches up with Intel's claim that 18A isn't that much more expensive than intel 7 and structural cost on Intel 4 being flatish to slightly below intel 7. Because I can sure as hell tell you N2 is MUCH more expensive to produce than N7.
So first. Density is often the biggest part of AC. From what I have seen from 2 decades of process technologies, the difference between the best and the rest on wafer cost isn't anywhere near as large as people make it out to be. Take a really good like for like comparison like GF and UMC. UMC is Taiwan based with some Singapore fabs, and they grew up in the same environment as TSMC with very similar process nodes. GF process nodes are from a different lineage and like 1/2 of the manufacturing is in the west. Operating margin between the two historically isn't very far apart. Much of TSMC's margin abnormally high margin is from TSMC's service and reputation, allowing for more premium pricing. Further evidence for that shows up as they left UMC in the dust and then left Samsung and GF in the dust, their GM/OM kept ricing as they became the only choice for leading edge. Now as good as the "rest", probably not.
When Intel showed AMD+TSMC margin vs Intel margin over time, they had better margins than the combined entity until 2016 (from here on out Intel's technology lead was gone). Matched margins until 2018 (AMD firmly on their feet). Comparable margins until 2019 (after this 10nm started making up greater and greater portions of Intel's sell through volume as ice lake was ramping). And margins didn't get way worse until 2022 (chip oversupply and subsequent utilization collapse as inventory was wound down and almost all of Intel's production is on 10nm). I don't know about you but I notice a common denominator here. And that common denominator isn't that all Intel processes are wildly cost ineffective. If it was Intel's GM would have been much lower back in "the glory days".
As for the CPU vs mobile APs. Yes, but also look at the products. Intel 14nm SOCs had nearly full node levels of worse xtors/mm^2 worse than Apple 20nm mobile APs. Was this simply because intel process = bad areal cost? No. Intel's chip designers chose to have 2x the metal layers, they chose to use the optional airgaps, and it was also their call to use tall cells for most of the SOC. When you look at say a 14nm chipset. Where the number of metal layers is reduced, no airgaps, and the HD logic cells are heavily used. That die cost starts looking far more TSMC like. Or in this case better than TSMC like since we are talking about TSMC 20nm vs intel 14nm.
Yeah, but that isn't huge volumes. And their custom ecosystems are ARM based. I doubt they want to re-write/port to a closed ecosytem with limited growth like x86.
Last edited:
