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Intel produced 30,000 wafers on ASML's high NA EUV

hskuo

Well-known member
Wow. It is mostly not like 30k full wafers, but it could be 30k wafer-step in Hi NA EUV machine. If it is 1k wafer per day, then the tool/tools have been up-running quite well. It is amazing.
1740437079474.png

1740437474584.png


 
Intel says new ASML machines are in production, with positive results

SAN JOSE, California (Reuters) - Intel on Monday said that the first two cutting-edge lithography machines from ASML Holding are "in production" at its factories, with early data indicating they are more reliable than earlier models.

At a conference in San Jose, California, Intel senior principal engineer Steve Carson said Intel has produced 30,000 wafers, the large discs of silicon that can yield thousands of computing chips, in a single quarter with ASML's high numerical aperture (NA) lithography machines.

Intel last year was the world's first chipmaker to take delivery of the machines, which are expected to produce smaller and faster computing chips than earlier ASML machines. The move was a shift in strategy for Intel, which lagged rivals in adopting the previous generation of extreme ultraviolet (EUV) lithography machines.

It took Intel seven years to put those earlier machines into full production, which contributed to it losing its lead to Taiwan Semiconductor Manufacturing Co. Intel struggled with the reliability of those previous EUV models in the initial stages of production.

However, Carson said ASML's new high NA machines are about twice as reliable as the earlier generation in initial testing.

"We're getting wafers out at a consistent rate, and that's a huge boon to the platform," Carson said.

The new ASML machines, which print features onto chips using beams of light, can also do the same work as earlier machines using fewer exposures, saving time and money.

Carson said early results at Intel's factories showed that the high NA machines can do what took earlier machines three exposures and about 40 processing steps with just one exposure and a "single digit" number of processing steps.

Intel has said it plans to use the high NA machines to help develop what it calls its 18A manufacturing technology, which is scheduled for mass production with a new generation of PC chip later this year.

It has said it plans to put the high NA machines into full production with its next generation of manufacturing technology called 14A, but has not given a mass production date for that technology.

 
"Intel has said it plans to use the high NA machines to help develop what it calls its 18A manufacturing technology, which is scheduled for mass production with a new generation of PC chip later this year.

It has said it plans to put the high NA machines into full production with its next generation of manufacturing technology called 14A, but has not given a mass production date for that technology."

Is this correct? Intel is using HNA-EUV to develop 18A?
 
"Intel has said it plans to use the high NA machines to help develop what it calls its 18A manufacturing technology, which is scheduled for mass production with a new generation of PC chip later this year.

It has said it plans to put the high NA machines into full production with its next generation of manufacturing technology called 14A, but has not given a mass production date for that technology."

Is this correct? Intel is using HNA-EUV to develop 18A?
I assume the article writer butchered the order of words and that they meant that 18A would be used to develop high-NA. This would be consistent with prior statements from Ann Kehleher and Mark Phillips that high-NA would be debugged on 18A. This could be like TSMC debugging immersion on 90nm before inserting it for its first commercial use at 40nm, or it could be like TSMC's limited productization of N7+ to derisk 2020's N6 and N5. I suspect which option depends on high-NA maturity. If things are very smooth then why not make a fully productized 18A-highNA derivative people can use if they want to and have 14A use more high-NA layers. If things are just okay keep that 18A derivative as a purely internal development vehicle and have 14A do a conservative high-NA insertion. And if things make a sudden and unexpected turn for the worst you can just use the original low-NA only 14A process that Intel showed off at IFS-DC 2024.
 
At a conference in San Jose, California, Intel senior principal engineer Steve Carson said Intel has produced 30,000 wafers, the large discs of silicon that can yield thousands of computing chips, in a single quarter with ASML's high numerical aperture (NA) lithography machines.
30000 wafers/qtr
 
However, Carson said ASML's new high NA machines are about twice as reliable as the earlier generation in initial testing.
This should be a general new generation vs older generation thing. 3800 model should be similar improvement over older models.
 
The new ASML machines, which print features onto chips using beams of light, can also do the same work as earlier machines using fewer exposures, saving time and money.

Carson said early results at Intel's factories showed that the high NA machines can do what took earlier machines three exposures and about 40 processing steps with just one exposure and a "single digit" number of processing steps.
If the "earlier" machines are the previous EUV NA, he might be talking about ~ 20 nm pitch.
imec had just released some results for 20 nm pitch: https://www.imec-int.com/en/press/imec-demonstrates-electrical-yield-20nm-pitch-metal-lines-obtained-high-na-euv-single, still rough as expected.

P20 roughness (imec).png

High-NA applications are more sensitive to blur, which reduces contrast and aggravates stochastic effects. https://frederickchen.substack.com/p/a-realistic-electron-blur-function

On the other hand, if he is talking about ~30 nm pitch, he could or should be talking about DUV machines. That's more steps but still strange to see those numbers. They must have some special spacer scheme or something.

Afterthought note: the 40 processing steps must be for 18A, incredible.
 
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I assume the article writer butchered the order of words and that they meant that 18A would be used to develop high-NA. This would be consistent with prior statements from Ann Kehleher and Mark Phillips that high-NA would be debugged on 18A. This could be like TSMC debugging immersion on 90nm before inserting it for its first commercial use at 40nm, or it could be like TSMC's limited productization of N7+ to derisk 2020's N6 and N5. I suspect which option depends on high-NA maturity. If things are very smooth then why not make a fully productized 18A-highNA derivative people can use if they want to and have 14A use more high-NA layers. If things are just okay keep that 18A derivative as a purely internal development vehicle and have 14A do a conservative high-NA insertion. And if things make a sudden and unexpected turn for the worst you can just use the original low-NA only 14A process that Intel showed off at IFS-DC 2024.
100% correct.

The news that came out seems confused and now people are extrapolating confusion. Next, we will be hearing about how Intel cornered the market on High NA and TSMC can't get them.
 
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