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Accordingly, on a scale of 1 to 5, where 1 is a fablet and 5 is a full fab, where is Intel currently vs. where are they heading? Like currently 4 and heading towards 2?
Intel 7 is a full chip fab. Intel 4 is a fablet. Intel 3 is a full chip fab. Intel 20A is a fablet. Intel 18A is a full chip fab. Since Intel is separating 14A and 10A in the graphic below I would guess that they will both be full chip fabs. The whole fablet concept is Intel's way of catching up to TSMC's marketing. Smoke and mirrors at its finest.
Cute but it is more like chiplet fabs sit on top of interposer fabs. Which is where the bottlenecks are.
If you look at what both Intel and AMD are doing at the high end their interposers are active, large chips providing infrastructure like cache and fabric (what used to be "bus") and memory and IO interfaces, not just passive wiring. Probably using an N-1 or N-2 process. We can expect to see something of the same from Nvidia who have just been doing giant but passive interposers so far.
And a logic chiplet tends to be bigger than a memory chip, so what would you call a memory fab?
Intel 7 is a full chip fab. Intel 4 is a fablet. Intel 3 is a full chip fab. Intel 20A is a fablet. Intel 18A is a full chip fab. Since Intel is separating 14A and 10A in the graphic below I would guess that they will both be full chip fabs. The whole fablet concept is Intel's way of catching up to TSMC's marketing. Smoke and mirrors at its finest.
In the old school design world we used to call them blocks. Multiple teams did digital blocks and assembled them to tape out a full chip. Now chiplets actually are die level blocks that you can stack together to make a chip.
How about this, a full fab does full chips and a fablet does chiplets?
Seriously is a chiplet with the same transistor count as a "chip" really a different achievement for a given node/fab?
I get they may have different circuit types but a CPU chiplet surely demonstrates all of the basics for node health, especially if shown at high frequency?
Seriously is a chiplet with the same transistor count as a "chip" really a different achievement for a given node/fab?
I get they may have different circuit types but a CPU chiplet surely demonstrates all of the basics for node health, especially if shown at high frequency?
Look at how AMD used chiplets for Rome. Some years ago, but the principle endures. Their CPU chiplets could use an early version of the PDK and needed only one kind of IO driver to be ready on TSMC 7, since the full suite of IO was on a different chip made with GF12. So AMD got to be one of the first customers to use TSMC 7.
Clearly this is still an interesting thing. Maybe few want to struggle with an early PDK, but many chiplets will be just fine without a full set of IO and many other specialized IP blocks not yet ready off the shelf. Look at how Amazon builds Graviton, taking a multicore off-the-shelf macro from ARM for their main chip and then connecting AMBA chip-to-chip to memory and PCIe interface chiplets in older process. Since ARM works together with fabs to bring up their cores early it makes sense to decouple from a full suite of IO which often has no scaling advantage anyway.
I dont have the exact details of tool limiters on 20A/18A. but for a technology you do first tool set and there is quantization can can be fairly large. So you dont normally build 500 WSPW.... even if thats what you want. 2000-3000 is more typical. Again.... its capacity, not wafer starts.
Side note: Intel is not planning Fablets. This will be part of the 18A/20A ramp paradox. Fablets are bad and high cost (except in development), Chiplets are Good. IMHO
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