intel Foundry EDA tool readiness

[hskuo]

 

[Daniel Nenni]

There are other EDA tools certified for Intel 18A. Remember, Intel is one of the big EDA customers for internal use so this is not a big challenge. IP is a challenge but Intel signed agreements with Synopsys, Cadence, and ARM and other key IP companies joined in.

Hopefully Intel will give us a foundry update on next week's call. I really hope customers will step up and make sure we have another trusted foundry to choose from at the leading edge.

 

[Paul2]

Intel

Is Intel a Synopsis shop these days?

I feel their own internal EDA usage practices will be forced upon their foundry clients.

 

[Daniel Nenni]

Is Intel a Synopsis shop these days?

I feel their own internal EDA usage practices will be forced upon their foundry clients.

They have always been. In fact, Intel used to be Synopsys' top customer. A very big emulator user.

 

[nghanayem]

Is Intel a Synopsis shop these days?

They do have a huge campus in Hillsboro so I would assume so.

I feel their own internal EDA usage practices will be forced upon their foundry clients.

Back in the days of BS, intel talked about moving to industry standard design tools to speed up development and so they could use external foundries. At CES intel also talked about how they threw out their we'll kindly call it artisanal chip design practices for Lioncove and Skymont. Lines up nicely with BS' tenure 3-6 years ago (2018-21).

 

[siliconbruh999]

They do have a huge campus in Hillsboro so I would assume so.

Back in the days of BS, intel talked about moving to industry standard design tools to speed up development and so they could use external foundries. At CES intel also talked about how they threw out their we'll kindly call it artisanal chip design practices for Lioncove and Skymont. Lines up nicely with BS' tenure 3-6 years ago (2018-21).

Better late than never i guess they made their IP way more Portable it was evident with Meteor Lake as well Crestmont on SOC and CPU Tile

 

[KevinK]

I feel their own internal EDA usage practices will be forced upon their foundry clients.

That was an indirect but complicated issue in their last foundry attempt. Even when commercial EDA tools were used and supported, Intel‘s own unique methodologies impinged on standard foundry flows using digital EDA tools. Some of the most vexing rough spots from 8-10 years ago:
* characterization - assumptions about design usage and methodology were baked into internal standard cells and especially the characterization. Moving to third party IP helped but that came a little later.
* routing rules - were far outside the norms for foundry flows. Lots of tricks for higher density a speed were not applicable for design styles outside of Intel’s constrained styles (i.e. GPUs).
* metal fill - live fill methodology added iterations to flow

I’m betting Intel has moved to a much more foundry-methodology-friendly flow, ever since they went to TSMC for some of their leading edge dies.